參數資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數: 69/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
66
Clock Divisor Register (default = 00h)
Type:
Read/Write
Bit Description
:
Bits [7:4]:
Reserved.
Bit 3:
RSTDRV. Reset Drive, valid only in PowerPC mode. When this bit is set, PCIRST# and
ISARST are enabled for 1 ms. This bit then clears (resets) itself.
Bits [2:0]:
Clock select (CLKSEL). This field selects the divisor for generating BCLK from PCICLK.
Combinations not listed are reserved.
Bit 2
Bit 1
Bit 0
0
0
0
=
4
0
0
1
=
3
0
1
0
=
2
1
0
0
=
6
1
0
1
=
8
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