參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 94/159頁
文件大小: 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
91
Scatter/Gather Command Registers (default = 000000h)
Function:
Each of these three registers controls the Scatter/Gather operation of DMA channels [7:5].
Type
:
Write only
Bit Description:
Bit 7:
IR13EOPSEL. IRQ13/EOP Select. If enabled via bit 6 of this register, bit 7 selects whether
EOP or IRQ13 is asserted at termination caused by a last buffer expiring. If bit 7 = 1, EOP is
asserted; otherwise IRQ13 is asserted.
Bit 6:
IRQ13EOPEN. IRQ13/EOP Programming Enable. If bit 6 = 1, it enables IRQ13/EOP
programming and allows initialization or modification of the Scatter/Gather termination handling
bits.
Bits [5:2]:
Reserved. Must be 0.
Bits [1:0]:
Scatter/Gather Commands.
Bit 1
0
Command
0
0
No Scatter/Gather operation.
0
1
Start Scatter/Gather.
1
0
Stop Scatter/Gather. This will halt a transfer immediately.
1
1
Reserved.
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