參數(shù)資料
型號： W83C554F
英文描述： W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述： W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)（南橋）
文件頁數(shù)： 32/159頁
文件大?。?/td> 3991K
代理商： W83C554F
W83C553F
The IDE interface is fully ANSI CAM compliant to the ATA Revision 3.0 and the ATA-2 specifications. Each storage
device on the two ports is individually programmable to select the desired command on and off times to support ATA defined
PIO MODES 0 through 2 and Multiword DMA MODE 0. Also supported are SFF PIO MODES 3, 4 and 5 (proposed) and
Multiword DMA MODES 1 and 2.
The devices supported are ATA compliant hard disks, tape drives, and CD ROMs. The W83C553F is compliant with the
emerging ATAPI Specification.
Two interrupt controllers can handle a total of 15 interrupt channels. IRQ0 is internally connected to OUT0, of the 82C54
counter/timer. Usually an interrupt is generated by the rising edge of IRQ. IRQ8 and IRQ13, however, are fixed to trigger
on the falling edge for direct connection to the real time clock interrupt or Pentium CPU floating point error signal. RX
4D0h and RX4D1h can be programmed to change the IRQs from edge sensitive to level sensitive interrupts. All external
IRQ lines are not internally pulled-up. I/O port and channel definition matches the IBM PC/AT requirement.
Types A, B, F DMA are supported by the W83C553F. Two integrated 82C37A DMA controllers each generate memory
addresses and control signals to transfer information between a peripheral device and memory, without CPU intervention.
Four DMA channels permit 8-bit peripheral device data transfers. Three channels permit 16-bit peripheral device data
transfers. During a DMA or master cycle, the CPU is held and the W83C553F takes control. Both DMA controllers support
scatter/gather transfer capability on all channels and 32-bit addressing.
The W83C553F has two basic operational states: reset and active. The reset state brings all internal logic to a known state,
and configures some chip features. The active state is the normal operating state that allows software to perform chip
configuration, access to the PCI and ISA register sets, and accessing of up to four IDE devices.
3.2
Active State
When active, the W83C553F will monitor all PCI bus cycles and respond to configuration and I/O cycles. The W83C553F
will always respond to configuration cycles when properly addressed but will always respond to I/O cycles, as indicated in
the internal configuration registers.
Configuration cycles are executed anytime the W83C553F IDSEL pin is asserted, a valid command is detected, and AD[1:0]
are "0" during the address phase. Configuration cycles are executed to program the W83C553F internal configuration
register sets. I/O cycles will only be executed when enabled as indicated in the configuration registers. I/O cycles are used to
transfer command/status and data to/from the IDE devices, as well as to program the bus master register set.
Electrical Specifications
WINBOND SYSTEMS LABORATORY
29
相關(guān)PDF資料
PDF描述
W83L519D Peripheral Miscellaneous
W86C451 UART
W86C452 UART
W86F3448D LC86F3548A
W86F3448M LC86F3548A
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W83C554FY 制造商:Nuvoton Technology Corp 功能描述:I/O Controller Phase Controller 制造商:Nuvoton Technology 功能描述:I/O Controller Phase Controller
W83E14 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:SYSMAC-C20 MANUAL DX CODE ZA
W83L177R 制造商:WINBOND 制造商全稱:Winbond 功能描述:100MHZ 2-DIMM SDRAM BUFFER FOR NOTEBOOK
W83L197R-16 制造商:WINBOND 制造商全稱:Winbond 功能描述:2-CHIP 100MHZ CLOCK FOR BX NOTEBOOK
W83L351 制造商:WINBOND 制造商全稱:Winbond 功能描述:ExpressCard⑩ Power Interface Switch
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*