參數(shù)資料
型號(hào): W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(biāo)(南橋)
文件頁數(shù): 119/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Bit [10:9]
Electrical Specifications
WINBOND SYSTEMS LABORATORY
116
DSTMG. These bits encode the timing of DEVSEL#. They are hardwired to 01b indicating the
support of medium DEVSEL# timing. This allows for support of fast back-to-back PCI bus
cycles. This will maximize the PCI bus bandwidth for PIO data transfer cycles.
MPE. This bit will be set when operating as a bus master and either the PERR# output is
driven low by the W83C553F or the target asserts PERR# and bit 6 of the Device Control
Register is set.
FBB. This bit will always be set. The W83C553F fully supports fast back to back transactions
to different targets.
These bits are reserved and are hardwired to logic 0b.
Bit 8:
Bit 7:
Bit [6:0]:
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