參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數(shù): 25/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Pin Descriptions
WINBOND SYSTEMS LABORATORY
22
Table 2-5 (Continued). ISA Bus Signals
Input/
Output
Description
Input/
Output
as an input during ISA master cycles.
Input/
Output
as input during ISA master cycles.
Output
Memory Read To Address Below 1M. An external pull-up resistor
is required.
Output
Memory Write To Address Below 1M. An external pull-up resistor
is required.
Input
Zero Wait State. This signal is used by ISA slaves to terminate a
transfer cycle before the default ready counter expires.
Input/
Output
is being transferred on SD[15:8].
Input/
Output
to indicate 16-bit transfer capability.
Input
I/O Cycle 16-Bit Select. This signal is used by I/O slaves to
indicate 16-bit transfer capability.
Input
I/O Channel Check. This assertion of this signal indicates an error
has occurred.
Pin Name
IOR#
Pin #
140
I/O Read. Act as an output during PCI master and DMA cycles and
IOW#
139
I/O Write. Act as an output during PCI master and DMA cycles and
SMEMR#
138
SMEMW#
137
ZWS#
132
SBHE#
174
System Byte High Enable. SBHE# is asserted to indicate that data
M16#
175
Memory Cycle 16-Bit Select. This signal is used by memory slaves
IO16#
177
IOCHK#
122
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