參數(shù)資料
型號： W83C554F
英文描述： W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述： W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標（南橋）
文件頁數(shù)： 124/159頁
文件大?。?/td> 3991K
代理商： W83C554F
W83C553F
Base Address Registers 0 through 3 (10h-13h, 14h-17h, 18h-1Bh, 1Ch-1Fh)
The W83C553F can be configured to support these Base Address Registers or to disable them. This can be useful in
configuring the device to operate in PCI systems that have various levels of configuration compatibility. Base Address
Registers 0 and 1 are used to control the primary IDE port I/O address locations. Base Address Registers 2 and 3 are used to
control the secondary IDE port I/O address locations. IOR[A:B]# and IOW[A:B]# are used with IDECS0# and IDECS1# to
access the primary and second ports. Note: A Base Address register does not contain a valid address when it is equal to "0".
Table 4-3
.
Base Address Register Mapping
Base
Address
Register
0
1F0h-1F7h
IDE_CS0#
1
3F6h
IDE_CS1#
2
170h-177h
IDE_CS0#
3
When P0N/L# bit in Programming Interface Register is set, Base Address Register 0,1 can be programmed for relocation to
any address within the 32 bit PCI I/O address space.
When P1N/L# bit in Programming Interface Register is set, Base Address Register 2,3 can be programmed for relocation to
any address within the 32 bit PCI I/O address space.
The default values of all the registers are located above.
When relocating the IDE ports, the normal procedure is to first program the Base Address Register with a value of FF FF FF
FFh. Next the register is read. Base Address Registers 0 and 2 will respond with a value of FF FF FF F9h indicating a
decode range of 8 bytes in I/O space, while 1 and 3 will respond with a value of FF FF FF FDh indicating a decode range of 4
bytes in I/O space. Although Base Address Registers 1 and 3 indicate a decode of 4 bytes, they will only claim cycles to byte
lane 2 (of 0 through 3) of the 4 byte range. This means that register accesses to 3F4h, 3F5h, 3F7h, 374h, 375h or 377h (or the
equivalent offset) will not be claimed or executed.
The W83C553F will only decode IDE port addresses if the IOEN bit of the Device Control Register is high and the IDE port
is enabled in the W83C553F function 1: IDE Control/Status Registers.
Electrical Specifications
WINBOND SYSTEMS LABORATORY
121
Address
Decode
IDE Chip
Select
Default When
Enabled
Value When
Programmed
FF FF FF FFh
00 00 03 F5h
00 00 01 71h
00 00 03 75h
00 00 01 F1h
FF FF FF F9h
FF FF FF FDh
FF FF FF F9h
FF FF FF FDh
376h
IDE_CS1#
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