參數(shù)資料
型號: W83C554F
英文描述: W83C554F Highly Integrated System I/O Controller for Power PC TM (South Bridge) & UltraDMA/33 IDE Controller QFP 208
中文描述: W83C554F高度集成的系統(tǒng)的I / O控制器的Power PC商標(南橋)
文件頁數(shù): 123/159頁
文件大?。?/td> 3991K
代理商: W83C554F
W83C553F
Electrical Specifications
WINBOND SYSTEMS LABORATORY
120
Latency Timer Register (default = 00h)
Function
:
This register specifies, in PCI bus clocks, the value of the latency timer when operating as a bus master.
Bits 0 through 2 are hardwired to a 0b. Bits 3 through 7 are programmable allowing a programmable
latency value in increments of 8 PCI clocks. The result is a timer granularity of eight clocks. This register
has a default value of 00h.
Type
: Read/Write
Bit Description
:
Bit [7:3]
High-order Timer Bits. Five programmable timer value bits.
Bit [2:0]
Low-order Timer Bits. Hardwire to ground for read-only 0b values.
Header Type Register (default = 80h)
Type:
Read only
Bit Description
:
Bits [7:0]:
This byte identifies the layout of bytes 10h through 3Fh in the configuration space. A default
value of 80h specifies the class codes shown in Table 6-1 of the PCI Specification.
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