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參數(shù)資料
| 型號(hào)： | VMX1C1020 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Versa Mix 8051 Mixed-Signal MCU |
| 中文描述： | 反之亦然混合8051混合信號(hào)微控制器 |
| 文件頁數(shù)： | 8/80頁 |
| 文件大?。?/td> | 3605K |
| 代理商： | VMX1C1020 |
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VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 8 of 80
F
IGURE
8: SFR
O
RGANIZATION
INTERNAL DATA
MEMORY SPACE
SFR SPACE -
PERIPHERALS
(DIRECT
ADDRESSING)
ADC
CONTROL
SPI BUS
DIFF
TRANSCEIVER
CLOCK
CONTROL
PERIPHERAL
INTERRUPTS
MAC
I/O CONTROL
I2C BUS
8051
PROCESSOR
PERIPHERALS
80H
FFH
Dual Data Pointers
The VMX51C1020 includes two data pointers.
The first data pointer (DPTR0) is mapped into
SFR locations 82h and 83h and the second data
pointer (DPTR1) mapped into SFR locations 84h
and 85h. The SEL bit in the data pointer select
register, DPS (SFR 86h), selects which data
pointer is active. When SEL = 0, instructions that
use the data pointer will use DPL0 and DPH0.
When SEL = 1, instructions that use the DPTR will
use DPL1 and DPH1. SEL is located in bit 0 of the
DPS (SFR location 86h - the remaining bits of SFR
location 86h are un-used.
All DPTR-related instructions use the currently
selected data pointer. In order to switch the active
pointer, toggle the SEL bit. The fastest way to do
so is to use the increment instruction (INC DPS).
The use of the two data pointers can significantly
increase the speed of moving large blocks of data
because only one instruction is needed to switch
from a source address and destination address.
The SFR locations and register representations
related to the dual data pointers are outlined as
follows:
T
ABLE
3:
(DPH0)
D
ATA
P
OINTER
H
IGH
0
-
SFR
83
H
15
14
13
12
DPH0 [7:0]
T
ABLE
4:
(DPL0)
D
ATA
P
OINTER
L
OW
0
-
SFR
82
H
7
6
5
4
DPL0 [7:0]
Bit
Mnemonic
Function
15-8
DPH0
Data Pointer 0 MSB
7-0
DPL0
Data Pointer LSB.
11
10
9
8
3
2
1
0
T
ABLE
5:
(DPH1)
D
ATA
P
OINTER
H
IGH
1
-
SFR
85
H
15
14
13
12
DPH1 [7:0]
11
10
9
8
T
ABLE
6:
(DPL1)
D
ATA
P
OINTER
L
OW
1
-
SFR
84
H
7
6
5
4
DPL1 [7:0]
3
2
1
0
Bit
15-8
7-0
Mnemonic
DPH1
DPL1
Function
Data Pointer 1 MSB.
Data Pointer 1 LSB.
T
ABLE
7:
(DPS)
D
ATA
P
OINTER
S
ELECT
R
EGISTER
-
SFR
86
H
7
6
5
0
0
0
Bit
Mnemonic
7-1
0
0
SEL
4
0
3
0
2
0
1
0
0
SEL
Function
Always zero
0 = DPTR0 is selected
1 = DPTR1 is selected
Used to toggle between both data
pointers
MPAGE Register
The MPAGE register controls the upper 8 bits of
the targeted address when the MOVX instruction is
used for external RAM data transfer. This allows
access to the entire external RAM content without
using the Data Pointer.
T
ABLE
8:
(MPAGE)
M
EMORY
P
AGE
-
SFR
CF
H
7
6
5
4
3
MPAGE [7:0]
User Flags
2
1
0
The VMX51C1020 provides an SFR register that
gives the user the ability to define software flags.
Each bit of this register is individually addressable.
This register may also be used as a general-
purpose storage location. Thus, the user flag
feature allows the VMX51C1020 to better adapt to
each specific application. This register is located at
SFR address F8h
T
ABLE
9:
(USERFLAGS)
U
SER
F
LAG
-
SFR
F8
H
7
6
5
4
UF7
UF6
UF5
UF4
3
2
1
0
UF3
UF2
UF1
UF0
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