
VMX51C1020
T
ABLE
21:
(MACCTRL2)
MULT/ACCU
U
NIT
C
ONTROL
R
EGISTER
2
-SFR
F1
H
7
6
MACCLR2 [2:0]
_________________________________________________________________________________________________
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page 19 of 80
5
4
MACOV32IE
3
-
2
-
1
0
MACOV16
MACOV32
Bit
7:5
Mnemonic
MACCLR[2:0]
Function
MULT/ACCU Register Clear
000 = No Clear
001 = Clear MACA
010 = Clear MACB
011 = Clear MACC
100 = Clear MACPREV
101 = Clear All MAC regs +
Overflow Flags
110 = Clear Overflow Flags only
MULT/ACCU 32-bit Overflow
IRQ Enable
-
-
16-bit Overflow Flag
0 = No 16 overflow
1 = 16-bit MULT/ACCU
Overflow occurred
32-bit Overflow Flag
1 = 32-bit MULT/ACCU
Overflow
This automatically loads the
MAC32OV register.
The MACOV32 can generate a
MULT/ACCU interrupt when
enabled.
4
MACOV32IE
3
2
1
-
-
MACOV16
0
MACOV32
MULT/ACCU Unit Data Registers
The
operand and result registers that serve to store
the numbers being manipulated in mathematical
operations. Some of these registers are uniquely
for addition (such as MACC) while others can be
used for all operations. The MULT/ACCU
operation registers are represented below.
MACA and MACB Multiplication
(Addition) Input Registers
MULT/ACCU
Data
registers
include
The MACA and MACB register serve as 16-bit
input operands when performing multiplication.
When the MULT/ACCU is configured to perform
32-bit addition, the MACA and the MACB
registers are concatenated to represent a 32-bit
word. In that case the MACA register contains
the upper 16-bit of the 32-bit operand and the
MACB contains the lower 16-bit
T
ABLE
22:
(MACA0)
MULT/ACCU
U
NIT
A
O
PERAND
,
L
OW
B
YTE
-
SFR
F2
H
7
6
5
4
MACA0 [7:0]
Bit
Mnemonic
Function
7:0
MACA0
Lower segment of the MACA
operand
T
ABLE
23:
(MACA1)
MULT/ACCU
U
NIT
A
O
PERAND
,
H
IGH
B
YTE
-
SFR
F3
H
7
6
5
4
MACA1 [15:8]
Bit
Mnemonic
Function
15:8
MACA1
Upper segment of the MACA
operand
T
ABLE
24:
(MACB0)
MULT/ACCU
U
NIT
B
O
PERAND
,
L
OW
B
YTE
-
SFR
F9
H
7
6
5
4
MACB0 [7:0]
Bit
Mnemonic
Function
7:0
MACB0
Lower segment of the MACB
operand
T
ABLE
25:
(MACB1)
MULT/ACCU
U
NIT
B
O
PERAND
,
H
IGH
B
YTE
-
SFR
FA
H
7
6
5
4
MACB1 [7:0]
Bit
Mnemonic
Function
Upper segment of the MACB
operand
MACC Input Register
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
7:0
MACB1
The MACC register is a 32-bit register used to
perform 32-bit addition.
It’s possible to substitute the MACPREV
Register for the MACC register or 0 in the 32-bit
addition.
T
ABLE
26:
(MACC0)
MULT/ACCU
U
NIT
C
O
PERAND
,
L
OW
B
YTE
-
SFR
EC
H
7
6
5
4
MACC0 [7:0]
Bit
Mnemonic
Function
Lower segment of the 32-bit addition
register
T
ABLE
27:
(MACC1)
MULT/ACCU
U
NIT
C
O
PERAND
,
B
YTE
1
-
SFR
ED
H
7
6
5
4
MACC1 [15:8]
Bit
Mnemonic
Function
Lower middle segment of the 32-bit
addition register
T
ABLE
28:
(MACC2)
MULT/ACCU
U
NIT
C
O
PERAND
,
B
YTE
2
-
SFR
EE
H
7
6
5
4
MACC2 [23:16]
Bit
Mnemonic
Function
Upper middle segment of the 32-bit
addition register
3
2
1
0
7:0
MACC0
3
2
1
0
15:8
MACC1
3
2
1
0
23:16
MACC2