參數(shù)資料
型號(hào)： VMX1C1020
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁(yè)數(shù)： 33/80頁(yè)
文件大小： 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 33 of 80
T
ABLE
54:
(CCL1)
C
OMPARE
/C
APTURE
R
EGISTER
1,
L
OW
B
YTE
-
SFR
C2
H
7
6
5
4
CCL1 [7:0]
T
ABLE
55:
(CCH1)
C
OMPARE
/C
APTURE
R
EGISTER
1,
H
IGH
B
YTE
-
SFR
C3
H
7
6
5
4
CCH1 [7:0]
T
ABLE
56:
(CCL2)
C
OMPARE
/C
APTURE
R
EGISTER
2,
L
OW
B
YTE
-
SFR
C4
H
7
6
5
4
CCL2 [7:0]
T
ABLE
57:
(CCH2)
C
OMPARE
/C
APTURE
R
EGISTER
2,
H
IGH
B
YTE
-
SFR
C5
H
7
6
5
4
CCH2 [7:0]
T
ABLE
58:
(CCL3)
C
OMPARE
/C
APTURE
R
EGISTER
3,
L
OW
B
YTE
-
SFR
C6
H
7
6
5
4
CCL3 [7:0]
T
ABLE
59:
(CCH3)
C
OMPARE
/C
APTURE
R
EGISTER
3,
H
IGH
B
YTE
-
SFR
C7
H
7
6
5
4
CCH3 [7:0]
Compare/Capture Data Line Width
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
The VMX51C1020 is capable of comparing and
capturing data using data lines up to 16 bits
wide. When comparing 2 registers or capturing
1 register, it is required to set the T2SIZE bit of
the T2CON register to 1. This adjusts the line
width to 8-bits.
When comparing two pairs of registers, for
example, CCH1 and CCL1 to TH2 and TL2, the
T2SIZE bit must be set to 0. This adjusts the line
width to 16 bits.
Timer2 Capture Modes
The Timer2 Capture Modes allow acquiring and
storing the 16-bit contents of Timer2 into a
Capture/Compare register following a MOV SFR
operation or the occurrence of an external event
on one of the CCU pins (described in the
following table).
Capture input
Timer 2 Capture triggering event
CCU0
High to Low Transition on CCU0
CCU1
Low to High Transition on CCU1
CCU2
Low to High Transition on CCU2
Timer2 capture is done without affecting Timer2
operation.
Each individual Compare and Capture Unit can
be configured for Capture Mode by configuring
the appropriate bit pair of the CCEN register.
The two Capture modes are Mode 0 and Mode
1.
Capture Mode 0
In Capture Mode 0, a transition on a given CCU
pin triggers the latching of Timer2 data into the
associated Compare/Capture register.
Capture Mode 1
In Capture Mode 1, a capture of the Timer2
value will occur upon writing to the Low Byte of
the chosen capture register.
Note:
On the VMX51C1020, the CCU3 input is
NOT pinned out.
F
IGURE
23:
T
IMER
2
C
APTURE
M
ODE
0
FOR
CRCL
AND
CRCH
B
LOCK
D
IAGRAM
Input
Clock
Reload
Data Bus
Data Bus
TL2
TH2
Data Bus
Data Bus
CRCL / CCLx
CRCH / CCHx
Data Latch
Data Latch
Write to CRCL, CCLx
Timer 2 interrupt
request
Capture
Mode 1
Capture
Mode 0
CCUx Pin
T2IF
The Capture modes can be especially useful for
external event duration calculation with the
ability to latch the timer value at a given time
(computation can then be performed at a later
time).
When operating in Capture Modes, the Compare
and Capture units don’t affect the VMX51C1020
Interrupts.
Timer2 Compare Modes
In Compare Mode, a Timer2 count value is
compared to a value that is stored in the
CCHxx/CCLx or CRCHx/CRCLx registers. If the
values compared match (i.e. when the pulse
changes state), a Compare/Capture interrupt is
generated, if enabled. Varying the value of the
CCHx/CCLx
or
CRCHx/CRCLx
variation of the rectangular pulse generated at
the output. This variation can be used to perform
pulse width modulation. See PWM in the
following section.
In order to activate the Compare Mode on one of
the four Compare Capture Units, the associated
COCAHx and COCALx bits must be set to 1 and
0, respectively
allows
a
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