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參數資料
| 型號： | VMX1C1020 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Versa Mix 8051 Mixed-Signal MCU |
| 中文描述： | 反之亦然混合8051混合信號微控制器 |
| 文件頁數： | 24/80頁 |
| 文件大?。?/td> | 3605K |
| 代理商： | VMX1C1020 |
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VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 24 of 80
VMX51C1020 Timers
The VMX51C1020 includes 3 general-purpose
timer/counters
o
Timer0
o
Timer1
o
Timer2
Timer0 and Timer1 are general purpose timers
that can operate as a timer with a clock rate
based on the system clock, or as an event
counter that monitosr events occurring on an
external timer input pin (T0IN for Timer 0 and
T1IN for Timer 1).
Timers 0 and Timer 1 are similar to the standard
8051 timers.
Apart from also being capabile of operating as a
timer based on a system clock or as an event
counter, Timer2 is also the heart of the PWM
counter outputs and the Compare and Capture
Units.
Each of the VMX51C1020’s timers has a
dedicated interrupt vector which can be
triggered when the Timers overflow.
Timer 0 and Timer 1
The VMX51C1020’s Timer0 and Timer1 are very
similar in their structure and operation. The
main difference being that Timer1 serves as a
baud rate generator for UART0 and it shares
some of its resources when Timer0 is used in
mode 3.
Timer0 and Timer1 each consist of a 16-bit
register for which the content is accessible as
two independent SFR registers: TLx and THx.
T
ABLE
39:
(TL0)
T
IMER
0
L
OW
B
YTE
-
SFR
8A
H
7
6
5
4
TL0 [7:0]
3
2
1
0
T
ABLE
40:
(TH0)
T
IMER
0
H
IGH
B
YTE
-
SFR
8C
H
7
6
5
4
TH0 [7:0]
3
2
1
0
T
ABLE
41:
(TL1)
T
IMER
1
L
OW
B
YTE
-
SFR
8B
H
7
6
5
4
TL1 [7:0]
3
2
1
0
T
ABLE
42:
(TH1)
T
IMER
1
H
IGH
B
YTE
-
SFR
8D
H
7
6
5
4
TH1 [7:0]
3
2
1
0
With the exception of their associated interrupts,
the configuration and control of Timer0 and
Timer1 is performed via the TMOD and TCON
SFR registers.
The following table shows the TCON special
function register of the VMX51C1020. This
register contains the Timer 0/1 overflow flags,
Timer 0/1 run control bits, interrupt 0/1 edge
flags, and the interrupt 0/1 interrupt type control
bits.
T
ABLE
43:
(TCON)
T
IMER
0,
T
IMER
1
T
IMER
/C
OUNTER CONTROL
-
SFR
88
H
7
6
TF1
TR1
3
2
IE1
IT1
Bit
Mnemonic
Function
7
TF1
Timer 1 overflow flag.
Set by hardware when Timer 1 overflows.
It is automatically cleared when the
Timer 1 interrupt is serviced.
This flag can also be cleared by software.
6
TR1
Timer 1 Run control bit.
TR1 = 0, Stop Timer 1
TR1 = 1, Start Timer 1
5
TF0
Timer 0 overflow flag.
Set by hardware when Timer 0 overflows.
It is automatically cleared when the
Timer 0 interrupt is serviced.
This flag can also be cleared by software.
4
TR0
Timer 0 Run control bit.
TR0 = 0, Stop Timer 0
TR0 = 1, Start Timer 0
3
IE1
Interrupt 1 edge flag.
This flag is set by hardware when falling
edge on external INT1 is observed.
It is cleared when interrupt is processed.
2
IT1
INT1 interrupt event type control bit.
IT1 = 0,
IT1 = 1,
1
IE0
INT0 edge flag configuration
Set by hardware when falling edge on
external pin INT0 is observed.
It is cleared when interrupt is processed.
0
IT0
INT0 interrupt event type control bit.
IT0 = 0,
IT0 = 1,
5
4
TF0
TR0
1
IE0
0
IT0
interrupt will be caused by
a Low Level on INT1
Interrupt will be caused by a
High to Low transition on INT1.
interrupt will be caused by
a Low Level on INT0
Interrupt will be caused by a
High to Low transition on INT0.
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