參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁(yè)數(shù)： 37/80頁(yè)
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 37 of 80
Serial UART Interfaces
The VMX51C1020 includes two serial UART
interface ports (UART0 and UART1). Each
serial port has a 10-bit timer devoted to baud
rate generation.
Both serial ports can operate in full duplex
mode. The VMX51C1020 also includes a
double buffer, enabling the UART to accept an
incoming word before the software has read the
previous value.
UART0 Serial Interface
The operation of UART0 of the VMX51C1020 is
similar to the standard 8051 UART.
UART0 can derive its clock source from a 10-bit
dedicated baud rate generator or from the
Timer1 overflow.
UART0’s Transmit and Receive buffers are
accessed through a unique SFR register named
S0BUF.
The UART0 S0BUF has a double buffering
feature on reception which allows accepting an
incoming word before the software has read the
previous value from the S0BUF.
T
ABLE
61:
(S0BUF)
S
ERIAL
P
ORT
0,
D
ATA
B
UFFER
-
SFR
99
H
7
6
5
4
S0BUF [7:0]
3
2
1
0
UART0 Control Register
UART0 configuration is performed mostly via the
S0CON SFR register located at address 98h.
T
ABLE
62:
(S0CON)
S
ERIAL
P
ORT
0,
C
ONTROL
R
EGISTER
-
SFR
98
H
7
6
S0M0
S0M1
5
4
MPCE0
R0EN
3
2
1
0
T0B8
R0B8
T0I
R0I
Bit
7
6
5
Mnemonic
S0M0
S0M1
MPCE
Function
Sets Serial Port Operating Mode
See Table
1 = Enables the multiprocessor
communication feature.
1 = Enables serial reception.
Cleared by software to disable
reception.
The 9
transmitted data bit in Modes
2 and 3. Set or cleared by the CPU,
depending on the function it
performs (parity check,
multiprocessor communication etc.)
In Modes 2 and 3, it is the 9
data bit
received. In Mode 1, if sm20 is 0,
RB80 is the stop bit. In Mode 0, this
bit is not used. Must be cleared by
software.
Transmit interrupt flag set by
hardware after completion of a serial
reception. Must be cleared by
software.
Receive interrupt flag set by
hardware after completion of a serial
reception. Must be cleared by
software.
4
R0EN
3
T0B8
2
R0B8
1
T0I
0
R0I
UART0 Operating Modes
UART0 can operate in four distinct modes,
which are defined by the SM0 and SM1 bits of
the S0CON register (see following table).
T
ABLE
63:
S
ERIAL
P
ORT
0
MODES
SM0
SM1
MODE
DESCRIPTION
0
0
0
Shift Register
0
1
1
8-bit UART
1
0
2
9-bit UART
1
1
3
9-bit UART
**
Note that the speed in mode 2 depends on SMOD bit in the Special
Function Register PCON when SMOD = 1 fclk/32
BAUD RATE
Fosc/12
Variable
Fclk/32 or /64
Variable
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