參數(shù)資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數(shù)： 30/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 30 of 80
F
IGURE
21:
T
IMER
2
AND
C
OMPARE
/C
APTURE UNIT
T2EXIE
SYSCLK
Interrupt Request
INPUT/OUTPUT Control
Timer 2
16-bit
Comparator
C16-bit
16-bit
Comparator
16-bit
Comparator
TL2
TH2
T2IF
Sync
T2EXIF
Reload
Sync
T2EX
T2IN
CRCL
CRCH
CCL1
CCL2
CCH1
CCL3
CCH3
Data
Latch
Data
Latch
Data
Latch
Data
Latch
Capture
Compare
Capture
Compare
Capture
Compare
COCAH1
Compare
Capture
Comp
Capture
Reload
Compare
Comp
Capture
Comp
Capture
Comp
Capture
Data
Latch
Enable
Enable
Enable
Enable
COCAH3
COCAH3
COCAH3
COCAH2
COCAH2
COCAH2
COCAH1
COCAH1
COCAH0
COCAH0
COCAH0
COCAH0
T2SIZE
÷2
÷12
÷2
T2PSM
T2PS
T2INxx
00
01
11
10
0
1
0
1
CCU0
INTCOMP3
INTCOMP2
P1.0-PWM0
P1.3-PWM3
Timer2 Clock Sources
As previously stated, Timer2 can operate in
Timer mode, in which case it derives its source
from the System Clock (SYSCLK) or it can be
configured as an event counter where the High
to Low transition on the T2IN input makes the
Timer 2 to increment.
The T2IN0 and T2IN1 bits of the T2CON register
serve to define the selected Timer2 input and
the operating mode of Timer2 (see following
table).
T
IMER
2
C
LOCK SOURCE
T2IN1
T2IN0
Selected Timer 2 input
0
0
Timer 2 Stop
0
1
Standard Timer mode using internal
clock with or without prescaler
1
0
External T2IN pin clock Timer2
1
1
Internal Clock is gated by the T2IN input
When T2IN = 0, the Timer2 stop
When in Timer mode, Timer2 derives its source
from the System Clock and the CLKDIVCTRL
register will affect Timer 2’s operation.
Timer 2 Stop
When both T2IN1 and T2IN0 bit are set to 0,
Timer2 is in STOP mode.
Timer2 Operating Modes
When the T2IN1 bit is set to 0 and the T2IN0 bit
is set to 1, Timer2 derives its source from the
internal pre-scaled clock or not, depending on
the T2PSM bit value.
Event Counter Mode
When operating in the Event Counter Mode, the
timer is incremented as soon as the external
signal T2IN transitions from a 1 to a 0. A
sample of the T2IN input is taken at every
machine cycle. Timer 2 is incremented in the
cycle following the one in which the transition
was detected.
Gated Timer Mode
which serves as the Timer2 clock source, is
gated by the external signal T2IN. In other
words, when T2IN is high, the internal clock is
allowed to pass through the AND gate. A low
value of T2IN will diable the clock pulse. This
provides the ability for an external device to
control Timer2’s operation or to use Timer2 to
monitor the duration of an event.
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