參數(shù)資料
型號(hào): VMX1C1020
廠商: Electronic Theatre Controls, Inc.
英文描述: Versa Mix 8051 Mixed-Signal MCU
中文描述: 反之亦然混合8051混合信號(hào)微控制器
文件頁(yè)數(shù): 7/80頁(yè)
文件大?。?/td> 3605K
代理商: VMX1C1020
VMX51C1020
_________________________________________________________________________________________________________
www.ramtron.com
page 7 of 80
Detailed Description
The
VMX51C1020’s architecture and peripherals.
F
IGURE
5: I
NTERFACE
D
IAGRAM FOR THE
VMX51C1020
following
sections
will
describe
the
VDD
AGND
VDDA
DGND
ADCI0
ADCI1
ADCI2
ADCI3
ISRCIN
ISRCOUT
SDI
SDO
SCK
SS-
CS0-
CS1-
CS2-
CS3-
RES-
INT0
INT1
VERSA
MIX
EXTERNAL A/D
INPUTS
CURRENT SOURCE
RESET
I/Os
EXTERNAL
INTERRUPTS
SPI
INTERFACE
+5V Digital
+5V Analog
T2IN
T2EX
T0IN
T1IN
TIMERS
I/O
COMPARE AND
CAPTURE UNITS
INPUTS
OP-AMP
POTENTIOMETERS
PWM
OUTPUTS
PWM0
PWM1
PWM2
PWM3
POT1A
POT1B
POT2A
POT2B
OPIN+
OPIN-
OPOUT
CCU0
CCU1
CCU2
OSC0 OSC1
DIGITAL
SWITCH
SW1A
SW1B
UART 0
UART 1
DIFFERENTIAL
TRANSCEIVER
UART1 DIFF.
TRANSCEIVER
J1708/RS-485 /
RS422
I2C
INTERFACE
SDA
UART 0
INTERFACE
UART 1
INTERFACE
SCL
F
IGURE
6: M
EMORY
O
RGANIZATION OF THE
VMX51C1020
INTERNAL DATA
MEMORY SPACE
EXTERNAL DATA
MEMORY SPACE
INTERNAL PROGRAM
MEMORY SPACE
8051
COMPATIBLE
μ-PROCESSOR
1KB
SRAM
SFR SPACE -
PERIPHERALS
(DIRECT
ADDRESSING)
56KB
FLASH
MEMORY
128 Bytes
RAM
(INDIRECT
ADDRESSING
03FFh
0000h
0000h
DFFFh
128 Bytes
RAM
(DIRECT &
INDIRECT
ADDRESSING)
FFh
80h
00h
FFh
80h
Memory Organization
Figure 6 shows the memory organization of the
VMX51C1020.
At power-up/reset, the code is executed from the
56Kx8 Flash memory mapped into the processor’s
internal Program space.
A 1KB block of RAM is also mapped into the
external data memory of the VMX51C1020. This
block can be used as general-purpose scratch pad
or storage memory. A 256 byte block of RAM is
mapped to the internal data memory space. This
block of RAM is broken into 2 sub-blocks, with the
upper block accessible via indirect addressing and
the lower block accessible via both direct and
indirect addressing.
The following figure describes the access to the
lower block of 128 bytes.
F
IGURE
7: L
OWER
128
B
YTES
B
LOCK
I
NTERNAL
M
EMORY
M
AP
LOWER 128 BYTES OF
INTERNAL DATA MEMORY
DIRECT
RAM
BIT-
ADDRESSABLE
REGISTERS
7Fh
30h
20h
18h
10h
08h
00h
BANK 3
BANK 2
BANK 1
BANK 0
00h
01h
10h
11h
REGISTER
BANK SELECT
The value of the
RS1, RS0 bits of
PSW SFR
Register (D0h)
defines the
selected R0 -R7
Register Bank
The SFR (Special Function Register) space is also
mapped into the upper 128 bytes of internal data
memory space. This SFR space is only accessible
using direct-access. The SFR space provides the
interface to all the on-chip peripherals. This
interfacing is illustrated in Figure 8.
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