參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁數(shù)： 45/80頁
文件大小： 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 45 of 80
SPI Interface
The VMX51C1020’s SPI peripheral is a highly
configurable and powerful interface enabling
high speed serial data exchange with external
devices such as A/Ds, D/Aa, EEPROMs, etc.
The SPI interface can operate as either a master
or a slave device. In master mode, it can control
up to 4 slave devices connected to the SPI bus.
The
following
lists
VMX51C1020’s SPI features.
o
Allows synchronous serial data transfers
o
Transaction size is configurable from 1-
32-bits and more.
o
Full duplex support
o
SPI Modes 0, 1, 2, 3 and 4 supported
(Full clock polarity and phase control)
o
Up to four slave devices can be
connected to the SPI bus when it is
configured in master mode
o
Slave mode operation
o
Data transmission speed is configurable
o
Double 32-bit buffers in transmission
and reception
o
3 dedicated interrupt flags
o
TX-Empty
o
RX Data Available
o
RX Overrun
o
Automatic/Manual control of the chip
selects lines.
o
SPI operation is not affected by the
clock control unit
The following provides a block diagram view of
the SPI Interface.
a
number
of
the
F
IGURE
29:
SPI
I
NTERFACE
B
LOCK
D
IAGRAM
Processor
SPI SFRs
SPI IRQs
VERSA MIX SPI
INTERFACE
Serial Data IN
Serial Data OUT
Serial Clock IN/OUT
SDI
SDO
SCK
CS0
CS1
CS2
CS3
SS
Chip Select Output
Chip Select Output
Chip Select Output
Slave Select Input
Chip Select Output
To Slave Device #1
To Slave Device #2
To Slave Device #3
To Slave Device #4
From Master Device
SPI Transmit/Receive Buffer
Structure
When receiving data, the first byte received is
stored in the SPIRX0 Buffer. As bits continue to
arrive, the data already present in the buffer is
shifted towards the least significant byte end of
the receive registers (see following figure).
For example (see following figure), assume the
SPI is about to receive 4 consecutive bytes of
data: W, X, Y and Z, where the first byte
received is byte W, The first received byte (W)
will be placed in the SPIRX0 register. Upon
reception of the next byte (X), the contents of
SPIRX0 will be shifted into SFR register SPIRX1
and byte X will be placed in the SPIRX0
registers. Following this same procedure, we
bytes W, X, Y and Z will end up in RX data
buffer registers SPIRX0, SPIRX1, SPIRX2 and
SPIRX3, respectively.
The case where the SDO and SDI pins are
shorted together is represented in the following
diagram.
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