參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁數(shù)： 35/80頁
文件大小： 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 35 of 80
F
IGURE
26:
C
OMPARE AND
C
APTURE
U
NIT
I
NTERRUPT CONTROL
COMPINT0
Interrupt
0
1
Interrupt Vector
0053h
SPI Rx &
RxOV INT
CCEN(1,0) = 1,0
COMPINT1
Interrupt
0
1
Interrupt Vector
005Bh
I2C INT
CCEN(3,2) = 1,0
COMPINT2
Interrupt
0
1
Interrupt Vector
0063h
MAC
Overflow INT
CCEN(5,4) = 1,0
COMPINT3
Interrupt
0
1
Interrupt Vector
006Bh
ADC & Port
Change INT
CCEN(7,6) = 1,0
Using Timer 2 for PWM Outputs
Configuring the Compare and Capture Units in
Compare Mode 0 allows PWM output generation
on the Port1 I/O pins. This mode can be used
for PWM applications such as:
o
D/A conversion
o
Motor control
o
Light control
o
Etc.
When one specific Compare and Capture unit is
configured for this mode, its associated I/O pin is
reserved for this operation only and any write
operation to the associated I/O pin of the P1
register will have no effect on it.
The following table shows the association
between the Compare and Capture Units,
associated registers and I/O pin
T
ABLE
60:
C
OMPARE AND
C
APTURE
U
NIT
PWM
ASSOCIATION
Compare
Capture
Unit
0
CRCH / CRCL
1
CCH1 / CCL1
2
CCH2 / CCL2
3
CCH3 / CCL3
PWM signal generation is derived from the
comparison result between the values stored
into the capture compare registers and the
Timer2 value.
When a digital value is written into one of the
Compare and Capture registers, a comparison is
performed between this register and the Timer2
value (providing that Timer2 is in Compare
Registers
I/O pin
P1.0
P1.1
P1.2
P1.3
Mode). As long as the value present in the
Compare and Capture register is greater than
the Timer2 value, the Compare unit will output a
logic low.
When the value of Timer2 equals the value of
the Compare and Capture register, the Compare
unit will change from a logic Low to a logic High.
The clock source for the PWM is derived from
Timer2; which is incremented at every signal
pulse of the appropriate source. The source is
selected by the T2IN1 and T2IN0 bits of the
T2CON register
The T2SIZE bit of the T2CON register allows
configuring the PWM output for 8 or 16-bit
operation. The Timer2 Size affects all the PWM
outputs.
When the Timer2 Size is 8-bits, the comparison
is performed between Timer2 and the LSB of the
Compare and Capture Unit register. The
resulting PWM resolution is 8-bit.
When the Timer2 Size is configured for 16-bit
operation, the comparison is performed between
Timer2 and the contents of the whole Compare
and Capture Unit register. The resulting PWM
resolution is 16-bits but the PWM frequency is
consequently low.
When the System clock is used as the Timer2
clock source, the PWM output frequency equals
the Timer2 overflow rate. Note that the
CLKDIVCTRL register contents affects Timer2
operation and thus, PWM output frequency.
T2CON
T2PSM
T2PS
1
X
1
x
0
0-12
0
0-12
0
1-24
0
1-24
The duty cycle of the PWM output is proportional
to the ratio of the Compare and Capture Unit
register’s content versus the Maximum Timer2
number of cycles before overflow: 256 or 65536,
depending on the T2SIZE bit value
Fosc
T2CON
T2CON
T2SIZE
0
1
1-8
0-16
1-8
0-16
Freq
PWM
112.5Hz
28.8KHz
4.8KHz
18.8Hz
2.4KHz
9.38Hz
14.74MHz
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