參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁數(shù)： 59/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 59 of 80
F
IGURE
39:
I
DEAL
A/D
C
ONVERTER
T
RANSFER
F
UNCTION
1111_1111_1111
1111_1111_1110
1111_1111_1101
1111_1111_1100
0000_0000_0000
0000_0000_0001
0000_0000_0010
0000_0000_0011
0V
XTVREF
1 LSB = XTVREF / 4096
OUTPUT
CODE
The A/D converter includes a system that
provides the ability to trigger automatic periodic
conversions of up to 10kHz without processor
intervention.
Once the conversion is complete, the A/D
system can activate an interrupt that can wake-
up the processor (assuming it has been put into
idle
mode)
or
automatically
processor clock to full speed.
The VMX51C1020 A/D converter can also be
configured to perform the conversion on one
specific channel or on four consecutive channels
(in round-robin fashion).
These features make the A/D adaptable for
many applications.
The
following
paragraphs
VMX51C1020’s A/D converter register features.
ADC Data Registers
throttle
the
describe
the
The ADC data registers hold the ADC
conversion results. The ADCDxLO register(s)
hold the 8 Least Significant Bits (LSBs) of the
conversion
results
while
register(s) hold the 4 Most Significant Bits (MSB)
of the conversion results.
the
ADCDxHI
T
ABLE
93:
(ADCD0LO)
ADC
C
HANNEL
0
D
ATA
R
EGISTER
,
L
OW
B
YTE
-
SFR
A6
H
Bit
Mnemonic
Function
7:0
ADCD0LO
ADC channel 0 low
T
ABLE
94:
(ADCD0HI)
ADC
C
HANNEL
0
D
ATA
R
EGISTER
,
H
IGH
B
YTE
-
SFR
A7
H
Bit
Mnemonic
Function
3:0
ADCD0HI
ADC channel 0 high
T
ABLE
95:
(ADCD1LO)
ADC
C
HANNEL
1
D
ATA
R
EGISTER
,
L
OW
B
YTE
-
SFR
A9
H
7
6
5
4
ADCD1LO [7:0]
Bit
Mnemonic
Function
7:0
ADCD1LO
ADC channel 1 low
T
ABLE
96:
(ADCD1HI)
ADC
C
HANNEL
1
D
ATA
R
EGISTER
,
H
IGH
B
YTE
-
SFR
AA
H
7
6
5
4
-
-
-
-
Bit
Mnemonic
Function
3:0
ADCD1HI
ADC channel 1 high
T
ABLE
97:
(ADCD2LO)
ADC
C
HANNEL
2
D
ATA
R
EGISTER
,
L
OW
B
YTE
-
SFR
AB
H
7
6
5
4
ADCD2LO [7:0]
Bit
Mnemonic
Function
7:0
ADCD2LO
ADC channel 2 low
T
ABLE
98:
(ADCD2HI)
ADC
C
HANNEL
2
D
ATA
R
EGISTER
,
H
IGH
B
YTE
-
SFR
AC
H
7
6
5
4
-
-
-
-
Bit
Mnemonic
Function
7:4
-
3:0
ADCD2HI
ADC channel 2 high
T
ABLE
99:
(ADCD3LO)
ADC
C
HANNEL
3
D
ATA
R
EGISTER
,
L
OW
B
YTE
-
SFR
AD
H
7
6
5
4
ADCD3LO [7:0]
Bit
Mnemonic
Function
7:0
ADCD3LO
ADC channel 3 low
T
ABLE
100:
(ADCD3HI)
ADC
C
HANNEL
3
D
ATA
R
EGISTER
,
H
IGH
B
YTE
-
SFR
AE
H
7
6
5
4
-
-
-
-
Bit
Mnemonic
Function
7:4
-
3:0
ADCD3HI
ADC channel 3 high
ADC Input Selection
3
2
1
0
3
2
1
0
ADCD1HI [3:0]
3
2
1
0
3
2
1
0
ADCD2HI [3:0]
-
3
2
1
0
3
2
1
0
ADCD3HI [3:0]
-
A/D conversions can be performed on a single
channel, sequentially on the four lower
channels, or sequentially on the four upper
channels of the ADC input multiplexer.
An input buffer is present on each of the four
external ADC inputs (ADIN0 to AIN3)
These buffers must be enabled before a
conversion can take place on the ADC AIN0-
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