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參數(shù)資料
| 型號： | VMX1C1020 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Versa Mix 8051 Mixed-Signal MCU |
| 中文描述： | 反之亦然混合8051混合信號微控制器 |
| 文件頁數(shù)： | 32/80頁 |
| 文件大?。?/td> | 3605K |
| 代理商： | VMX1C1020 |
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VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 32 of 80
Timer2 Setup Example
In order to use Timer2, one must first set up and
configure the module (see following code
example).
//---------------------------------------------------------------------------
// Sample C code to setup Timer 2
//---------------------------------------------------------------------------
//
(…)
PROGRAM INITIALIZATION OMITTED
at 0x100 void main(void){
// TIMER 2 & Interrupt setup
DIGPWREN = 0x80;
T2CON = 0x01;
TL2 = 0xE0;
TH2 = 0xFF;
IEN0 |= 0x80;
IEN0 |= 0x20;
do{
}while(1);
}//end of main()
//---------------------------------------------------------------------------
// Timer 2 Interrupt Function
//---------------------------------------------------------------------------
void int_timer_2 (void) interrupt 5
{
IEN0 &= 0x7F;
/*------------------------*/
/*Interrupt code here*/
/*------------------------*/
IEN0 |= 0x80;
}
Timer2 Special Modes
// Enable Timer2,
// Set timer 2 to OSC/12
// Enable all interrupts
// Enable interrupt Timer 2
//wait for Timer 2 interrupt
// Disable all interrupts
// Enable all interrupts
For general timing/counting operations, the
VMX51C1020’s Timer2 includes 4 Compare and
Capture units that can be used to monitor
specific events and serve to drive PWM outputs.
Each Compare and Capture unit provides three
specific operating modes that are controlled by
the CCEN register. These 3 modes are:
o
Compare Modes Enable.
o
Capture on write into CRCL/CCLx registers.
o
Capture on transitions at CCU input pins
level.
T
ABLE
51:
(CCEN)
C
OMPARE
/C
APTURE
E
NABLE
R
EGISTER
-SFR
C9
H
7
6
COCAH3
COCAL3
3
2
COCAH1
COCAL1
The CCEN register bits are grouped in pairs of
COCAHx/COCALx bits. Each pair corresponds
to one Compare and Capture Unit. The
Compare and Compare unit operating mode vs.
the configuration bit is described in the following
table.
5
4
COCAH2
COCAL2
1
0
COCAH0
COCAL0
Bit
Function
Compare and Capture mode
for CRC register
Compare/capture disabled
Capture on a falling edge at
pin CCU0 (1 cycle)
Compare enabled (PWM0)
Capture on write operation
into register CRC1
Compare/capture mode for
CC register 1
Compare/capture disabled
Capture on a rising edge at
pin CCU1 (2 cycles)
Compare enabled (PWM1)
Capture on write operation
into register CCL1
Compare/capture mode for
CC register 2
Compare/Capture disabled
Capture on a rising edge at
pin CCU2 (2 cycles)
Compare enabled (PWM2)
Capture on write operation
into register CCL2
Compare/Capture mode for
CC register 3
Compare/capture disabled
N/A - CCU3 not pinned out
Compare enabled (PWM)
Capture on write operation
into register CCL3
Mnemonic
COCAH0
Mnemonic
COCAL0
0
0
0
1
1
1
0
1
COCAH1
COCAL1
0
0
0
1
1
1
0
1
COCAH2
COCAL2
0
0
0
1
1
1
0
1
COCAH3
COCAL3
0
0
1
1
0
1
0
1
This
operation of each Compare and Capture Unit.
Compare/Capture & Reload Registers
allows
individual
configuration
and
Each Compare and Capture Unit has a specific
16-bit
register
accessible
addresses.
Note
that
the
CRCHx/CRCLx
associated with Compare/Capture Unit 0 are the
only ones that can be used to perform a reload
of Timer2 operation.
The following tables describe the different
registers that may be captured or compared to
the value of Timer2.
T
ABLE
52:
(CRCL)
C
OMPARE
/R
ELOAD
/C
APTURE
R
EGISTER
,
L
OW
B
YTE
-
SFR
CA
H
7
6
5
4
CRCL [7:0]
T
ABLE
53:
(CRCH)
C
OMPARE
/R
ELOAD
/C
APTURE
R
EGISTER
,
H
IGH
B
YTE
-
SFR
CB
H
7
6
5
4
CRCH
[7:0]
via
two
SFR
registers
3
2
1
0
3
2
1
0
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