參數資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數： 75/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 75 of 80
Watchdog Timer
The VMX51C1020’s Watchdog Timer is used to
monitor program operation and reset the
processor in the case where the program code
would not be able to refresh the Watchdog
before its timeout period has lapsed. This can
come about from an event that results in the
Program Counter executing faulty or incorrect
code and inhibiting the device from doing its
intended job.
The Watchdog Timer consists of a 15-bit counter
composed of two registers (WDTL and WDTH)
and a reload register (WDTREL). See following
figure.
F
IGURE
47:
W
ATCH
D
OG
T
IMER
÷16
÷2
0
7
Control Logic
0
7
8
14
WDTREL
WDTH
WDTL
WDTR
SYSCLK ÷ 12
WDTR
(Refresh)
WDTS
(Start)
The WDTL and WDTH registers are not
accessible from the SFR register. However the
WDTREL register makes it possible to load the
upper 6 bits of the WDTH register.
The PRES bit of the WDTREL register selects
the Clock prescaler that is fed into the Watchdog
Timer.
When PRES = 0, the clock prescaler = 24
When PRES = 1, the clock prescaler = 384
T
ABLE
127:
(WDTREL)
W
ATCHDOG
T
IMER
R
ELOAD
R
EGISTER
-
SFR
D9
H
7
6
5
4
PRES
WDTREL [6:0]
Bit
Mnemonic
Function
7
PRES
Pre-scaler select bit. When set, the
Watchdog is clocked through an
additional divide-by-16 pre-scaler.
6-0
WDTREL
7-bit reload value for the high-byte
of the Watchdog timer. This value
is loaded into the WDT when a
refresh is triggered by a
consecutive setting of bits WDT
and SWDT.
3
2
1
0
T
ABLE
128:
(IP0)
I
NTERRUPT
P
RIORITY
R
EGISTER
0
-
SFR
B8
H
7
6
UF8
WDTSTAT
Bit
Mnemonic
Function
7
UF8
User Flag bit
6
WDTSTAT
Watchdog timer status flag. Set to 1
by hardware when the watchdog
timer overflows. Must be cleared
manually
5
IP0.5
Timer 2
5
4
3
2
1
0
IP0 [5:0]
Port1
Change
-
-
ADC
4
3
2
IP0.4
IP0.3
IP0.2
UART0
Timer 1
External
INT1
Timer 0
Interrupt
External
INT0
MULT/ACCU
I2C
SPI RX
availlable
SPI TX
Empty
External
INT 0
-
1
IP0.1
-
0
IP0.0
UART1
The WDTSTAT bit of the IP0 register is the
Watchdog status flag. This bit is set to 1 by the
hardware whenever a Watchdog Timer overflow
occurs. This bit must be cleared manually.
Setting-up the Watchdog Timer
Control of the Watchdog Timer’s is enabled by
the following bits:
Bit
Location
WDOGEN
DIGPWREN.6
WDTR
IEN0.6
WDTS
IEN1.6
In order for the Watchdog to begin counting, the
user must set the WDOGEN bit (bit 6) of
DIGPWREN register, as follows:
MOV
DIGPWREN,#x1xxxxxxB
Role
Watchdog timer Enable
Watchdog timer refresh flag
Watchdog Timer Start bit
;x=0 or 1 depending
;of other peripherals
;to enable
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