參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁(yè)數(shù)： 41/80頁(yè)
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 41 of 80
UART1 Serial Interface
The UART1 serial interface is based on a subset
of UART0. It provides two operating modes and
its clock source is derived exclusively from a
dedicated 10-bit baud rate generator.
The UART1 Transmit and Receive buffers are
accessed via SFR register S1BUF.
T
ABLE
72:
(S1BUF)
S
ERIAL
P
ORT
1,
D
ATA
B
UFFER
-
SFR
C1
H
7
6
5
4
S1BUF [7:0]
As is the case with UART0, UART1 includes a
double buffering feature in order to avoid
overwriting of the receive register.
UART1 Control Register
3
2
1
0
UART1 is controlled by the S1CON register. The
following table provides a description of the
UART1 Control Register.
T
ABLE
73:
(S1CON)
S
ERIAL
P
ORT
1,
C
ONTROL
R
EGISTER
-
SFR
C0
H
7
6
S1M
Reserved
3
2
T1B8
R1B8
Bit
Mnemonic
Function
7
S1M
Operation mode Select
6
Reserved
-
5
MPCE1
1 = Enables multiprocessor
communication feature.
4
R1EN
If set, enables serial reception.
Cleared by software to disable
reception.
3
T1B8
The 9
transmitted data bit in mode
A. Set or cleared by the CPU,
depending on the function it performs
(parity check, multiprocessor
communication, etc.)
2
R1B8
In Mode A, it is the 9
th
data bit
received. In Mode B, if SM21 is 0,
RB81 is the stop bit. Must be cleared
by software.
1
T1I
Transmit interrupt flag, set by
hardware after completion of a serial
transfer. Must be cleared by software
0
R1I
Receive interrupt flag, set by
hardware after completion of a serial
reception. Must be cleared by
software
5
4
MPCE1
R1EN
1
0
T1I
R1I
UART1: Operating Modes
The VMX51C1020 UART1 has two operating
Modes, A and B, which provide 9 or 8-bit
operation, respectively (see following table).
T
ABLE
74:
UART1
M
ODES
SM
0
1
UART1 - Mode A
MODE
A
B
DESCRIPTION
9-bit UART
8-bit UART
BAUD
RATE
Variable
Variable
In this Mode, 11 bits are transmitted or received.
These 11 bits are composed of:
o
A start bit (logic low),
o
8 bits of data (LSB first),
o
A programmable 9
th
bit,
o
Stop bit (logic high).
As in Mode 2 and 3 of UART0, the 9
th
bit is used
for parity. For data transmission, the TB81 bit of
the S1CON register holds the 9
th
bit. In the case
of reception, the 9
th
bit will be captured into the
R1B8 bit of the S1CON register.
UART1 - Mode B
In this Mode, 10 bits are transmitted and consist
of:
o
A start bit (logic low)
o
8 bits of data (LSB first);
o
A stop bit (logic high).
Received data (8-bit) is read via the S1BUF
register. Reception is completed once the stop
bit sets the R1B8 flag in the S1CON register.
UART1 - Baud Rate Generator
As previously mentioned, UART1’s clock source
is derived from a dedicated 10-bit baud rate
generator module.
The S1REL registers are used to adjust the
baud rate of UART1.
T
ABLE
75:
(S1RELL)
UART1,
R
ELOAD
R
EGISTER
,
L
OW
B
YTE
-
SFR
BE
H
7
6
5
4
S1RELL [7:0]
T
ABLE
76:
(S1RELH)
UART
1,
R
ELOAD
R
EGISTER
,
H
IGH
B
YTE
-
SFR
BF
H
7
6
5
4
S1RELH [7:0]
3
2
1
0
3
2
1
0
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