參數(shù)資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數(shù)： 61/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 61 of 80
ADC Clock Source Configuration
A/D converter derives its clock source from the
main VMX51C1020 clock. The frequency of the
ADC clock should be set between 250kHz to
1.25MHz
Configuration
of
the
frequency is done by adjusting the value of the
ADCCLKDIV register. The following equation is
used to calculate the ADC reference clock value.
ADC Clock Reference Equation:
ADC Clk ref = f
4x (ADCCDIV +1)
The ADC conversion requires 111 ADC clock
cycles to perform the conversion on one
channel.
The following table provides recommended
ADCCLKDIV register values versus conversion
rate. The numbers given are conservative
figures and derived from a 14.74MHz clock
ADCCLKDIV
0x02
0x03
0x05
0x07
0x08
0x09
0x0B
0x0D, 0x0E, 0x0F
* The maximum conversion rate is for the single
channel condition. If the conversion is
performed on 4 channels, divide the maximum
conversion rate by 4. For example to perform
the conversion at 2.5KHz on four channels, the
ADCCLKDIV register should be set to 0x02 (4x
2500Hz =10KHz)
T
ABLE
103:
(ADCCLKDIV)
ADC
C
LOCK
D
IVISION
C
ONTROL
R
EGISTER
-
SFR
95
H
7
6
5
4
ADCCLKDIV [7:0]
Bit
Mnemonic
7:0
ADCCLKDIV[7:0]
ADC
clock
source
Maximum Conv. Rate*
10500 Hz
8000 Hz
5000 Hz
4000 Hz
3500 Hz
3200 Hz
2500 Hz
2200 Hz
3
2
1
0
Function
ADC clock divider
ADC Conversion Rate Configuration
The VMX51C1020’s ADC conversion rate, when
configured in continuous mode is defined by the
24-bit A/D Conversion Rate register that serves
as the time base for triggering the ADC
conversion process.
The following equation is used to calculate the
value of the conversion rate.
Conversion Rate Equation:
Conversion rate registers value (24-bit) = f
OSC
The conversion rate register is accessible using
three SFR registers as follows:
T
ABLE
104:
(ADCCONVRLOW)
ADC
C
ONVERSION
R
ATE
R
EGISTER
L
OW
B
YTE
-
SFR
A3
H
Bit
Mnemonic
Function
7:0
ADCCONVRLOW
Conversion rate low byte
T
ABLE
105:
(ADCCONVRMED)
ADC
C
ONVERSION
R
ATE
R
EGISTER
M
ED
B
YTE
-
SFR
A4
H
Bit
Mnemonic
Function
7:0
ADCCONVRMED
Conversion rate medium byte
T
ABLE
106:
(ADCCONVRHIGH)
ADC
C
ONVERSION
R
ATE
R
EGISTER
H
IGH
B
YTE
-
SFR
A5
H
Bit
Mnemonic
Function
7:0
ADCCONVRHIGH
Conversion rate high byte
The following table provides examples of typical
values versus conversion rate.
ADC conv. rate register value.
Conversion
Rate
Fosc= 14.74MHz
1Hz
10Hz
100Hz
1kHz
2.5kHz
5kHz
8kHz
10kHz
Conv_Rate
E10000h
168000h
024000h
003999h
00170Ah
000B85h
000733h
0005C2h
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