參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁(yè)數(shù)： 68/80頁(yè)
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 68 of 80
Interrupt Status Flags
The IRCON register is used to identify the
source of an interrupt. Before exitingthe
interrupt service routine, the IRCON register bit
that corresponds with the serviced interrupt
should be cleared.
T
ABLE
117:
(IRCON)
I
NTERRUPT
R
EQUEST
C
ONTROL
R
EGISTER
-
SFR
91
H
7
6
T2EXIF
T2IF
3
2
I2CIF
SPIRXIF
Bit
Mnemonic
Function
7
T2EXIF
Timer 2 external reload flag
This bit informs the user
whether an interrupt has been
generated from T2EX, if the
T2EXIE is enabled.
6
T2IF
Timer 2 interrupt flag
5
ADCIF /
COMPINT3
flag/ port 0 change.
/ COMPINT3
4
MACIF /
COMPINT2
request flag / COMPINT2
3
I2CIF /
COMPINT1
/ COMPINT1
2
SPIRXIF /
COMPINT0
Overrun / / COMPINT0
1
SPITXIF
TX empty flag SPI
0
Reserved
Reserved
Interrupt Priority Register
5
4
ADCIF
MACIF
1
0
SPITXIF
Reserved
A/D converter interrupt request
MULT/ACCU unit interrupt
I
C interrupt request flag
RX available flag SPI + RX
All of the VMX51C1020’s interrupt sources are
combined into groups with four levels of priority.
These groups can be programmed individually
to one of the four priority levels: from Level0 to
Level3 with Level3 being the highest priority.
The IP0 and IP1 registers serve to define the
specific priority of each of the interrupt groups.
By default, when the IP0 and IP1 registers are at
reset state 00h, the natural priority order of the
interrupts shown previously are in force.
T
ABLE
118:
(IP0)
I
NTERRUPT
P
RIORITY
R
EGISTER
0
-
SFR
B8
H
7
6
UF8
WDTSTAT
Bit
Mnemonic
Function
7
UF8
User Flag bit
6
WDTSTAT
Watchdog timer status flag. Set to 1
by hardware when the watchdog
timer overflows. Must be cleared
manually
5
IP0.5
Timer 2
5
4
3
2
1
0
IP0 [5:0]
Port1
Change
-
-
ADC
4
3
2
IP0.4
IP0.3
IP0.2
UART0
Timer 1
External
INT1
Timer 0
Interrupt
External
INT0
MULT/ACCU
I2C
SPI RX
available
SPI TX
Empty
External
INT 0
-
1
IP0.1
-
0
IP0.0
UART1
Table 119: (IP1) Interrupt Priority Register 1 - SFR B9h
7
6
5
-
-
Bit
Mnemonic
Function
7
-
-
6
-
-
5
IP1.5
Timer 2
4
3
IP1 [5:0]
2
1
0
Port1
Change
-
-
ADC
4
3
2
IP1.4
IP1.3
IP1.2
UART0
Timer 1
External
INT1
Timer 0
Interrupt
External
INT0
MULT/ACCU
I2C
SPI RX
available
SPI TX
Empty
External
INT 0
-
1
IP1.1
-
0
IP1.0
UART1
Configuring the IP0 and IP1 registers makes it
possible to change the priority order of the
peripheral interrupts in order give higher priority
to a given interrupt that belongs to a given
group.
T
ABLE
120:
I
NTERRUPT
G
ROUPS
Bit
Interrupt Group
IP1.5, IP0.5
Timer 2
Port1
Change
-
-
ADC
IP1.4, IP0.4
IP1.3, IP0.3
IP1.2, IP0.2
UART0
Timer 1
External
INT1
Timer 0
Interrupt
External
INT0
MULT/ACCU
I2C
SPI RX
available
SPI TX
Empty
External
INT 0
-
IP1.1, IP0.1
-
IP1.0, IP0.0
UART1
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