參數(shù)資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數(shù)： 67/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 67 of 80
T
ABLE
115:
(IEN1)
I
NTERRUPT
E
NABLE
1
R
EGISTER
-SFR
E8
H
7
6
T2EXIE
SWDT
5
4
ADCPCIE
MACOVIE
3
2
1
0
I2CIE
SPIRXOVIE
SPITEIE
reserved
Bit
7
Mnemonic
T2EXIE
Function
T2EX interrupt Enable
0 = Disable
1 = Enable
Watchdog timer start/refresh flag.
Set to activate/refresh the watchdog
timer. When directly set after setting
WDT, a watchdog timer refresh is
performed. Bit SWDT is reset.
ADC and Port change interrupt
0 = Disable
1 = Enable
MULT/ACCU Overflow 32 bits
interrupt
0 = Disable
1 = Enable
I2C Interrupt
0 = Disable
1 = Enable
SPI Rx avail + Overrun
0 = Disable
1 = Enable
SPI Tx Empty interrupt
0 = Disable
1 = Enable
6
SWDT
5
ADCPCIE
4
MACOVIE
3
I2CIE
2
SPIRXOVIE
1
SPITEIE
0
reserved
T
ABLE
116:
(IEN2)
I
NTERRUPT
E
NABLE
2
R
EGISTER
-
SFR
9A
H
7
6
5
-
-
-
Bit
Mnemonic
Function
7-1
-
0
S1IE
UART 1 Interrupt
0 = Disable UART 1 Interrupt
1 = Enable UART 1 Interrupt
4
-
3
-
2
-
1
-
0
S1IE
-
Timer2 Compare Mode Impact on
Interrupts
The SPI RX (and RXOV), I
2
C, MULT/ACCU and
ADC Interrupts are shared with the four Timer2
Compare and Capture Unit interrupts.
When the Compare and Capture Units of Timer2
are configured in Compare Mode via CCEN
register, the Compare and Capture unit takes
control of one interrupt vector as shown below.
F
IGURE
43:
C
OMPARE
C
APTURE
I
NTERRUPT
S
TRUCUTRE
COMPINT0
Interrupt
0
1
Interrupt Vector
0053h
SPI Rx &
RxOV INT
CCEN(1,0) = 1,0
COMPINT1
Interrupt
0
1
Interrupt Vector
005Bh
I2C INT
CCEN(3,2) = 1,0
COMPINT2
Interrupt
0
1
Interrupt Vector
0063h
MAC
Overflow INT
CCEN(5,4) = 1,0
COMPINT3
Interrupt
0
1
Interrupt Vector
006Bh
ADC & Port
Change INT
CCEN(7,6) = 1,0
The impact of this is that the corresponding
peripheral interrupt, if enabled, will be blocked.
The output signal from the comparison module
will be routed to the Interrupt system and the
control lines will be dedicated to the Compare
and Capture unit.
This interrupt control “take over” is specific to
each individual Compare and Capture unit. For
example if Compare and Capture Unit number 2
is configured to generate a PWM signal on P1.2,
the MULT/ACCU overflow interrupt, if enabled,
will be dedicated to the Compare and Capture
Unit number 2 and the SPI, I
2
C and ADC
interrupts won’t be affected.
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