參數(shù)資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數(shù)： 46/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 46 of 80
F
IGURE
30 :
SPI
I
NTERFACE
R
ECEIVE
T
RANSMIT
S
CHEMATIC
W
Z
Y
X
RX Data Buffer
TX Data Buffer
Close-Up View of how the bits within
the byte is placed after it has been
received
7
6
5
4
3
2
1
0
MSBit
LSBit
Bytes are Shifted 1 byte position
at a time each time a new byte is
received
W
Z
Y
X
RX Data Buffer
TX Data Buffer
0
1
2
3
4
5
6
7
LSBit
MSBit
BEFORE A RECEPTION
SPITX3
SPIRX0
SPITX0
SPIRX3
AFTER A RECEPTION
First Byte to be
Transmitted
SPIRX3
SPITX3
SPIRX0
SPITX0
First Byte Received is
Placed in the least
significant byte register
msb
msb
lsb
lsb
lsb
lsb
msb
msb
SPIRX2
SPIRX1
SPITX2
SPITX1
SPITX2
SPITX1
SPIRX2
SPIRX1
When using the SPI Interface, it is important to
keep in mind that a transmission is started when
the SPIRX3TX0 register is written to.
From an SFR point of view, the transmission
and reception buffers of the SPI interface
occupy the following addresses.
T
ABLE
78:
(SPIRX3TX0)
SPI
D
ATA
B
UFFER
,
L
OW
B
YTE
-
SFR
E1
H
7
6
5
4
SPIRX3TX0 [7:0]
Bit
Mnemonic
Function
SPITX0
SPI Transmit Data Bits 7:0
7-0
SPIRX3
SPI Receive Data Bits 31:24
T
ABLE
79:
(SPIRX2TX1)
SPI
D
ATA
B
UFFER
,
B
YTE
1
-
SFR
E2
H
7
6
5
4
SPIRX2TX1 [15:8]
Bit
Mnemonic
Function
SPITX1
SPI 1 Transmit Data Bits 15:8
15:8
SPIRX2
SPI Receive 1 Data Bits 23:16
3
2
1
0
3
2
1
0
T
ABLE
80:
(SPIRX1TX2)
SPI
D
ATA
B
UFFER
,
B
YTE
2
-
SFR
E3
H
7
6
5
SPIRX1TX2 [23:16]
Bit
Mnemonic
SPITX2
22:16
SPIRX1
T
ABLE
81:
(SPIRX0TX3)
SPI
D
ATA
B
UFFER
,
H
IGH
B
YTE
-
SFR
E4
H
7
6
5
SPIRX0TX3 [31:24]
Bit
Mnemonic
SPITX3
31:24
SPIRX0
SPI Control Registers
4
3
2
1
0
Function
SPI Transmit Data Bits 23:16
SPI Receive Data Bits 15:8
4
3
2
1
0
Function
SPI Transmit Data Bits 31:24
SPI Receive Data Bits 7:0
The SPI Control registers are used to define:
o
SPI operating speed
(Master mode)
o
Active Chip Select output
(Master mode)
o
SPI clock Phase
(Master/Slave modes).
o
SPI clock Polarity
(Master/Slave modes).
T
ABLE
82:
(SPICTRL)
SPI
C
ONTROL
R
EGISTER
-
SFR
E5
H
7
6
SPICK [2:0]
3
2
SPICS_0
SPICKPH
Bit
Mnemonic
Function
7:5
SPICK[2:0]
SPI Clock control
000 = OSC Ck Div 2
001 = OSC Ck Div 4
010 = OSC Ck Div 8
011 = OSC Ck Div 16
100 = OSC Ck Div 32
101 = OSC Ck Div 64
110 = OSC Ck Div 128
111 = OSC Ck Div 256
4:3
SPICS[1:0]
Active CS line in Master Mode
00 = CS0- Active
01 = CS1- Active
10 = CS2- Active
11 = CS3- Active
2
SPICKPH
SPI Clock Phase
1
SPICKPOL
SPI Clock Polarity
0 – CK Polarity is Low
1 – CK Polarity is High
0
SPIMA_SL
Master / -Slave
1 = Master
0 = Slave
5
4
SPICS_1
1
0
SPICKPOL
SPIMA_SL
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