參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁(yè)數(shù)： 71/80頁(yè)
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 71 of 80
UART0 and UART1 Interrupt Example
The following program examples demonstrate
how to initialization the UART0 and UART1
interrupts.
//-------------------------------------------------------------------------------
// Sample C code for UART0 and UART1 interrupt example
//-------------------------------------------------------------------------------
#pragma TINY
#include <vmixreg.h>
// --- function prototypes
void txmit0( unsigned char charact);
void txmit1( unsigned char charact);
void uart1Config(void);
void uart0ws0relcfg(void);
// - Constants definition
sbit UART_TX_EMPTY = USERFLAGS^1;
//---------------------------------------------------------------------------
// MAIN FUNCTION
//---------------------------------------------------------------------------
at 0x0100 void main (void) {
// Enable and configure the UART0 & UART1
uart0ws0relcfg();
//Configure UART0
uart1Config();
//Configure UART1
//*** Configure the interrupts
IEN0 |= 0x91;
//Enable UART0 Int + enable all int
IEN2 |= 0x01;
//Enable UART1 Interrupt
do
{
}while(1);
//Wait for UARTs interrupts
// End of main()...
//---------------------------------------------------------------------------
// INTERRUPT ROUTINES
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// UART0 interrupt
//
// Retrieve character received in S0BUF and transmit it
// back on UART0
// //-------------------------------------------------------------------------
void int_uart0 (void) interrupt 4 {
IEN0 &= 0x7F;
//--- The only UART0 interrupt source is Rx...
txmit0(S0BUF);
//disable All interrupts
// Return the character
//received on UART0
S0CON = S0CON & 0xFC;
IEN0 |= 0x80;
}// end of UART0 interrupt
//clear R0I & T0I bits
// enable all interrupts
//---------------------------------------------------------------------------
// UART1 interrupt
//
// Retrieve character received in S1BUF and transmit it
// back on UART1
// //---------------------------------------------------------------------------
void int_uart1 (void) interrupt 16 {
IEN0 &= 0x7F;
//--- The only UART1 interrupt source is Rx...
txmit1(S1BUF);
//disable All interrupts
// Return the character
// received on UART1
// clear both R1I & T1I bits
// enable all interrupts
}// end of UART1 interrupt
Note:
S1CON = S1CON & 0xFC;
IEN0 |= 0x80;
See UART0 / UART1 section for configuration examples and
TXMITx functions
Interrupt on P1 Change
The VMX51C1020 includes an Interrupt on Port
change feature, which is available on the Port1
pins of the VMX51C1020.
This feature is like having eight extra external
interrupt inputs sharing the ADC interrupt vector
at address 006Bh and can be very useful for
applications such as switches, keypads, etc.
To activate this interrupt, the bits corresponding
to the pins being monitored must be set in the
PORTIRQEN register. The ADCPCIE bit in the
IEN1 register must be set as well as the EA bit
of the IEN0 register.
T
ABLE
123:
(PORTIRQEN)
P
ORT
C
HANGE
IRQ
C
ONFIGURATION
-
SFR
9F
H
7
6
P17IEN
P16IEN
3
2
P13IEN
P12IEN
Bit
Mnemonic
Function
7
P17IEN
Port 1.7 IRQ on change enable
0 = Disable
1 = Enable
6
P16IEN
Port 1.6 IRQ on change enable
0 = Disable
1 = Enable
5
P15IEN
Port 1.5 IRQ on change enable
0 = Disable
1 = Enable
4
P14IEN
Port 1.4 IRQ on change enable
0 = Disable
1 = Enable
3
P13IEN
Port 1.3 IRQ on change enable
0 = Disable
1 = Enable
2
P12IEN
Port 1.2 IRQ on change enable
0 = Disable
1 = Enable
1
P11IEN
Port 1.1 IRQ on change enable
0 = Disable
1 = Enable
0
P10IEN
Port 1.0 IRQ on change enable
0 = Disable
1 = Enable
The PORTIRQSTAT register monitors the
occurrence of the Interrupt on port change.
This register serves to define which P1 pin has
changed when an interrupt occurs.
5
4
P15IEN
P4IEN
1
0
P11IEN
P10IEN
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