參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁(yè)數(shù)： 54/80頁(yè)
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 54 of 80
I
2
C Interface Interrupts
The I
2
C interface has a dedicated interrupt
vector located at address 0x5B. Three flags
(see below) share the I
2
C interrupt vector and
can be used to monitor the I
2
C interface status
making it possible to activate the I
2
C interrupt.
I2CTXEMP
:
Is set to 1 when the transmit buffer is
empty
Is set to 1 when data byte reception
completes
.
Is set to 1 if a new byte reception
completes before the previous data in
the reception buffer is read, resulting in
a data collision.
I2CRXAV:
I2CRXOV:
These flags can all trigger the I
2
C interrupt if
their corresponding bit in the I2CCONFIG
register is set to one.
In the case where more than one of these flags
can activate an I
2
C interrupt, the interrupt
service routine is left to figure out which
condition generated the interrupt.
Note that the I2CRXAV, I2CTXEMP and
I2CRXOV flags can still be polled if their
corresponding interrupt enable flag is cleared.
Therefore they can still be used to monitor
status.
Master I
2
C Operation
In Master mode, the VMX51C1020 I
2
C interface
controls the I
2
C bus transfers. In order to
configure the I
2
C interface as a Master, the
I2CMASTER bit of the I2CCONFIG register
must be set to one.
Once the I
2
C interface is configured, sending
data to a Slave device connected to the bus is
done by writing the data into the I2CRXTX
register.
Before sending data to a Slave device, a byte
containing the target device’s chip ID and
Read/Write bit must be sent to it.
A master mode data read is triggered by reading
the I2CRXAV (bit 1) of the I2CIRQSTAT
register. The data is present on the I2CRXTX
register when the I2CRXAV bit is set.
Reading the value of the I2CRXTX register
resets the I2CRXAV bit. Once started, the I
2
C
byte read process will continue until the Master
generates a STOP condition.
When the I
2
C interface is configured as a
Master, setting the I2CMSTOP bit of the
I2CCONFIG register to a 1 will result in the I
2
C
interface generating a STOP condition after the
reception of the next byte.
In Master Mode, it’s possible to manually control
the operation of the acknowledged timing when
receiving data. To do this, you must first set the
I2CMANACK bit of the I2CCONFIG register to 1.
Then, once you have received a byte, you can
manually control the acknowledge level by
clearing or setting the I2CMANACK bit.
Note:
The VMX51C1020 I
2
C Interface is not
compatible with the I
2
C multi-master
mode.
Slave I
2
C Operation
The VMX51C1020 I
2
C interface can be
configured as a Slave by clearing the
I2CMASTER bit of the I2CCONFIG register.
In Slave mode, the VMX51C1020 has no control
over the rate or timing of the data exchange that
occurs on the I
2
C bus. Therefore, in Slave
mode,
it
is
preferable
transactions using the I
2
C interrupts.
The I2CMASKID bit, when set, will configure the
Slave device to mask the received ID byte and
receive the data directly. This is useful when
only two devices are present on the I
2
C bus.
Note:
When
the
transmitting data in Slave mode, it will
continually transmit the value present in
the I
2
C transmit register as long as the
Master provides the clock signal or until
the Master device generates a STOP
condition
to
manage
the
VMX51C1020
starts
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