參數資料
型號: VMX1C1020
廠商: Electronic Theatre Controls, Inc.
英文描述: Versa Mix 8051 Mixed-Signal MCU
中文描述: 反之亦然混合8051混合信號微控制器
文件頁數: 34/80頁
文件大?。?/td> 3605K
代理商: VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 34 of 80
When the Compare Mode is enabled, the
corresponding output pin value is under the
control of the internal timer circuitry.
On the VMX51C1020, two Compare Modes are
possible. In both modes, the new value arrives
at port pin 1 in the same clock cycle as the
internal compare signal is activated. The T2CM
of the T2CON register defines the Compare
Mode and is described in the following
paragraphs.
Compare Mode 0
A functional diagram of Compare Mode 0 is
shown below. A comparison is made between
the 16-bit value of the Compare/Capture
registers and the TH2, TL2 registers. When the
Timer2 value exceeds the value stored in the
CRCH, CRCL / CCHx, CCLx registers, a high
compare
signal
is
Compare/Capture interrupt is
enabled. If T2SIZE = 1, the comparison is made
between the TL2 and CRCL/CCLx register.
This compare signal is then propagated to the
pin corresponding P1.x Pin(s) and to the
associated COMPINTx interrupt (if enabled).
The corresponding P1.x pin is reset when a
Timer2 overflow occurs.
generated
and
a
activated if
F
IGURE
24:
T
IMER
2
C
OMPARE
M
ODE
0
B
LOCK
D
IAGRAM
Comparator
TH2
TL2
Timer 2
CRCH,
CCHX
CRCL,
CCLX
Overflow
Timer 2
Interrupt
Reset
Register
Compare
Signal
P1.0-
PWM0
Set
Register
P1.1-
PWM1
P1.2-
PWM0
P1.3-
PWM0
COMPxINT
Interrupt
Compare Mode 1
When a given Compare Capture unit is
operating in Mode 1, any write operations to the
corresponding output register of the port P1.x
(x=0 to3) will not appear on the physical port pin
until the next compare match occurs.
As is the case in Compare Mode 0, the
Compare signal in Mode 1 can also generate an
interrupt (if enabled).
The figure below shows the operating structure
of a given Capture Compare unit operating in
Compare Mode 1.
F
IGURE
25:
T
IMER
2
C
OMPARE
M
ODE
1
B
LOCK
D
IAGRAM
Comparator
TH2
TL2
Timer 2
CRCH,
CCHX
CRCL,
CCLX
Overflow
Timer 2
Interrupt
Compare
Signal
P1.0-
PWM0
Data
Latch
Shadow Register
Output Register
Port Register
Circuit
COMPxINT
Interrupt
P1.1-
PWM1
P1.2-
PWM2
P1.3-
PWM3
Timer 2 Compare Mode Interrupt
Configuration of the Compare and Capture Units
for the “Compare Mode” through the CCEN
register has an impact on the Interrupt structure
of the VMX51C1020. In that specific mode
each Compare Capture Unit takes control of one
interrupt line.
When using the PWM output device, some care
must be excercised to avoid other peripheral
interrupts
from
being
mechanism.
blocked
by
this
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