參數(shù)資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數(shù)： 60/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 60 of 80
AIN3 inputs. These buffers are enabling by
setting the corresponding bits of the lower nibble
(AIEN [3:0]) of the INMUXCTRL register to 1.
T
ABLE
101:
(INMUXCTRL)
A
NALOG
I
NPUT
M
ULTIPLEXER
C
ONTROL
R
EGISTER
-
SFR
B5
H
7
6
5
4
-
ADCINSEL [2:0]
Bit
Mnemonic
Function
7
-
6:4
ADCINSEL[2:0]
ADC Input Select
000 - AIN0
001 - AIN1
010 - AIN2
011 - AIN3
100 - OPOUT
101 - VSR
110 - ISRCIN
111 - ISRCOUT
3:0
AINEN[3:0]
Analog Input Enable
The upper four bits of the INMUXCTRL register
are used to define the channel on which the
conversion will take place when the ADC is set
to perform the conversion on one specific
channel.
ADC Control Register
3
2
1
0
AINEN [3:0]
-
The ADCCTRL register is the main register used
for control and operation of the ADC.
T
ABLE
102:
(ADCCTRL)
ADC
C
ONTROL
R
EGISTER
-
SFR
A2
H
7
6
ADCIRQCLR
XVREFCAP
3
2
ADCIE
ONECHAN
Bit
Mnemonic
Function
7
ADCIRQCLR
ADC interrupt clear
Writing 1 Clears interrupt
6
XVREFCAP
Always keep this bit at 1
5
Reserved = 1
Keep this bit = 1
4
ADCIRQ
Read ADC Interrupt Flag
Write 1 generate ADC IRQ
3
ADCIE
ADC interrupt enable
2
ONECHAN
1 = Conversion is performed on
one channel
Specified ADCINSEL
0 = Conversion is performed on
4 ADC channels
1
CONT
1 = Enable ADC continuous
conversion
0
ONESHOT
1 = Force a single conversion
on 1 or 4 channels
ADC Continuous/One Shot Conversion
5
1
4
ADCIRQ
1
0
CONT
ONESHOT
The CONT bit sets the ADC conversion mode.
When the CONT bit is set to 1, the ADC will
implement continuous conversions at a rate
defined by the Conversion Rate register.
When the CONT bit is set to 0, the A/D operates
in “One Shot” mode, initiating a conversion when
the ONESHOT bit of the ADCCONTRL register
is set.
ADC One Channel/ Four Channel Conversion
The VMX51C1020’s ADC includes a feature that
renders it possible to perform a conversion on
one specific channel or on four consecutive
channels.
This feature minimizes the load on the processor
when reading more than one ADC input is
required.
The ONECHAN bit of the ADCCTRL register
controls this feature. When the ONECHAN is
set to 1, the conversion will take place on the
channel selected by the INMUXCTRL register.
Once the conversion is completed, the result will
be put into the ADCD0LO and ADCD0HI
registers
When the ONECHAN bit is set to 0, the
conversion, once triggered, will be done
sequentially
on
four
conversion results will be placed into the
ADCDxLO and ADCDxHI registers.
Bit 6 of the INMUXCTRL register controls
whether the conversion will take place on the
four upper channels of the input multiplexer or
the 4 lower channels.
channels
and
the
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