參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁(yè)數(shù)： 52/80頁(yè)
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 52 of 80
I2C Interface
The VMX51C1020 includes an I2C compatible
communication interface that can be configured
in Master mode or in Slave mode.
I
2
C Control Registers
The I2CRXTX SFR register is used to retrieve
and transmit data on the I
2
C interface.
T
ABLE
86:
(I2CRXTX)
I2C
D
ATA
B
UFFER
-
SFR
DE
H
7
6
5
4
I2CRXTX [7:0]
Bit
Mnemonic
Function
I2C Data Receiver / Transmitter
buffer
The I2CCONFIG register serves to configure the
operation of the VMX51C1020 I
2
C interface.
The following table describes the I2CCONFIG
register bits.
T
ABLE
87:
(I2CCONFIG)
I2C
C
ONFIGURATION
-
SFR
DA
H
7
6
I2CMASKID
I2CRXOVIE
3
2
I2CMANACK
I2CACKMODE
Bit
Mnemonic
Function
7
This is used to mask the chip ID
when you have only two devices.
Therefore in a transaction, rather
that receiving the chip ID first,
you will receive the first packet of
data.
6
I2CRXOVIE
enable
5
I2CRXDAVIE
I2C Receiver available interrupt
enable
4
I2CTXEMPIE
I2C Transmitter empty interrupt
enable
3
I2CMANACK
1= Manual acknowledge line
goes to 0
0= Manual acknowledge line
goes to 1
2
I2CACKMODE
Used only with Master Rx, Master
Tx, and Slave Rx.
1= Manual Acknowledge on
0= Manual Acknowledge off
1
I2CMSTOP
I2C Master receiver stops at next
acknowledge phase. (read during
data phase)
0
I2CMASTER
I2C Master mode enable
1= I2C interface is Master
0= I2C interface is Slave
3
2
1
0
7:0
I2CRXTX[7:0]
5
4
I2CRXDAVIE
I2CTXEMPIE
1
0
I2CMSTOP
I2CMASTER
I2CMASKID
I2C Receiver overrun interrupt
The I2CIRQSTAT register provides the status of
the I
2
C interface operation and monitors the I
2
C
bus status.
T
ABLE
88:
(I2CIRQSTAT)
I2C
I
NTERRUPT
S
TATUS
-
SFR
DD
H
7
6
I2CGOTSTOP
I2CNOACK
3
2
I2CIDLE
I2CRXOV
Bit
Mnemonic
This means that the slave
has received a stop (this bit is
read only). Reset only when
the master begins a new
transmission.
Flag that indicates that no
acknowledge has been
received. Is reset at the start
of the next transaction
5
I2CSDA
Value of SDA line.
5
4
I2CSDA
I2CDATACK
1
0
I2CRXAV
I2CTXEMP
Function
7
I2CSGOTSTOP
6
I2CNOACK
4
I2CDATACK
Data acknowledge phase.
3
2
1
0
I2CIDLE
I2CRXOV
I2CRXAV
I2CTXEMP
Indicates that I2C is idle
I2C Receiver overrun
I2C Receiver available
I2C Transmitter empty
The I2CCHIPID register holds the VMX51C1020
I
2
C interface ID as well as the status bit that
indicates if the last byte monitored on the I
2
C
interface was destined for the VMX51C1020 or
not.
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