參數(shù)資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數(shù)： 76/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 76 of 80
The value written into the WDTREL register
defines the Delay Time of the Watchdog Timer
asfollows:
WDT delay when the WDTREL bit 7 is cleared
WDT Delay = 24*[ 32768–(WDTREL(6:0) x 256)]
Fosc
WDT delay when the WDTREL bit 7 is set
WDT Delay = 384*[ 32768–(WDTREL(6:0) x 256)]
Fosc
The following table provides WDT reload values
and their corresponding delay times
Fosc
WDTREL
14.74MHz
00h
14.74MHz
4Fh
14.74MHz
CCh
Note: The value present in the CLKDIVCTRL
Register affects the Watchdog Timer Delay time.
The above equations and examples assume that
the CLKDIVCTRL register content is 00h
Starting the Watchdog Timer
WDT Delay
53.3ms
20.4ms
347ms
To start the Watchdog timer using the hardware
automatic start procedure, the WDTS (IEN1)
and WDTR (IEN0) bits must be set. The
Watchdog will begin to run with default settings,
i.e. all registers will be set to zero.
;*** Do a Watchdog Timer Refresh / Start sequence
SETB
IEN0.6
;Set the WDTR bit first
SETB
IEN1.6
;Then without delay set the
;WDTS bit
When the WDT registers enter the state 7FFFh,
the asynchronous signal, WDTS will become
active. This signal will set bit 6 in the IP0 register
and trigger a reset.
To prevent the Watchdog Timer from resetting
the VMX51C1020, you must reset it periodically
by clearing the WDTR and, immediately
afterwards, clear the WDTS bit.
As a security feature to prevent inadvertent
clearing of the Watchdog timer, no delay
(instruction) is allowed between the clearing of
the WDTR and the WDTS bits.
a) Watchdog Timer refresh example 1:
*** The Simple way ***
MOV
IEN0,#x1xxxxxxB
;DIRECT WRITE THAT SET BIT
;WDTR (x = 0 or 1)
;DIRECT WRITE THAT SET BIT
;WDTS (x = 0 or 1)
MOV
IEN1,#x1xxxxxxB
In the case where the program makes use of the
interrupts, it is recommended to deactivate
interrupts before the Watch Dog refresh is
performed and reactivate them afterwards.
b) Watch Dog Timer refresh example 2:
*** If Interrupts are used: ***
CLR
IEN0.7
;Deactivate the interrupt
MOV
A,IEN0
;Retrieve IEN0 content
ORL
A,#01000000B
;set the bit 6 (WDTR)
XCH
A,R1
;Store IENO New Value
MOV
A,IEN1
;Retrieve IEN1 content
ORL
A,#01000000B
;Set bit 6, (WDTS)
MOV
IEN0,R1
; Set WDTR BIT
MOV
IEN1,A
;Set WDTS BIT
SETB
IEN0.7
;Reactivate the Interrupts
Watchdog Timer Reset
To determine whether the Reset condition was
caused by the Watchdog Timer, the state of the
WDTSTAT bit of the IP0 register should be
monitored. On a standard power on reset
condition, this bit is cleared.
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