參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁數(shù)： 66/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 66 of 80
VMX51C1020 Interrupts
The VMX51C1020 is a highly integrated device
incorporating a vast number of peripherals for
which a comprehensive set of 29 interrupt
sources sharing 12 interrupt vectors is available.
Most of the VMX51C1020 peripherals can
generate an interrupt, providing feedback to the
MCU core that an event has occurred or a task
has been completed.
The following features are key VMX51C1020
interrupt features.
o
Each
digital
VMX51C1020 has an interrupt channel.
o
The SPI, UARTs and I2C all have event
specific flag bits.
o
When the processor is in IDLE mode, an
interrupt may be used to wake it up.
o
The processor can run at full speed
during interrupt routines.
The following table summarizes the interrupt
sources, natural priority and the associated
interrupt vector addresses of the VMX51C1020.
T
ABLE
113:
I
NTERRUPT SOURCES AND NATURAL PRIORITY
Interrupt
Reserved
INT0
UART1
TIMER 0
SPI Tx
INT1
SPI RX & SPI RX OVERRUN
/ COMPINT0
TIMER 1
I2C (Tx, Rx, Rx Overrun)
/ COMPINT1
UART0
MULT/ACCU 32bit Overflow /
COMPINT2
TIMER 2: T2 Overflow, T2EX
ADC and interrupt on Port 1
change (8 int.) / COMPINT3
It is also possible to program the interrupts to
wake-up the processor from an IDLE condition
or force its clock to throttle up to full speed when
an interrupt condition occurs.
peripheral
on
the
Interrupt Vector
0E43h
0003h
0083h
000Bh
004Bh
0013h
0053h
001Bh
005Bh
0023h
0063h
002Bh
006Bh
Interrupt Enable Registers
The following tables describe the interrupt
enable registers their associated bit functions:
T
ABLE
114:
(IEN0)
I
NTERRUPT
E
NABLE
R
EGISTER
0
-
SFR
A8
H
7
6
EA
WDT
3
2
T1IE
INT1IE
Bit
Mnemonic
Function
7
EA
General Interrupt control
0 = Disable all Enabled interrupts
1 = Authorize all Enabled interrupts
6
WDT
Watchdog timer refresh flag. This bit
is used to initiate a refresh of the
watchdog timer. In order to prevent
an unintentional reset, the watchdog
timer the user must set this bit
directly before SWDT.
5
T2IE
Timer 2 Overflow / external Reload
interrupt
0 = Disable
1 = Enable
4
S0IE
Uart0 interrupt.
0 = Disable
1 = Enable
3
T1IE
Timer 1 overflow interrupt
0 = Disable
1 = Enable
2
INT1IE
External Interrupt 1
0 = Disable
1 = Enable
1
T0IE
Timer 0 overflow interrupt
0 = Disable
1 = Enable
0
INT0IE
External Interrupt 0
0 = Disable
1 = Enable
5
4
T2IE
S0IE
1
0
T0IE
INT0IE
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