參數(shù)資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數(shù)： 53/80頁
文件大小： 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 53 of 80
The reset value of this register is 0x42,
corresponding to an I
2
C Chip ID of 0x21. The
chip ID value of the VMX51C1020 can be
dynamically changed by writing the desired ID
into the I2CCHIPID register (see following table).
T
ABLE
89:
(I2CCHIPID)
I2C
C
HIP
ID
-
SFR
DC
H
7
6
5
4
3
I2CID [6:0]
Bit
Mnemonic
7:1
I2CID[6:0]
The value of this chip’s ID
Read Only and is used only in
slave mode.
0:The .ID received corresponds
to the I2CID
1: The ID received do not
correspond to the I2CID
The I2WID bit is “read only” and used only in
Slave mode and is an indicator of whether the
transaction is targeted to the VMX1020 device.
If the device ID sent by the Master device
corresponds to the I2CID value stored in the
I2CCHIPID, the I2WID bit will be cleared to 0 by
the I2C module. If the transaction was destined
for another I2C slave device, the I2WID bit will
be set to 1.
The I2WID value is valid at the moment the
device ID transmission from the master device
on the I
2
C bus has completee.
In the case where the I
2
C RX available interrupt
is activated, once the device ID is received, an
I
2
C RX available interrupt will be triggered. The
interrupt service routine should then monitor the
I2WID bit in order to establish if the transaction
is destined for this VMX1020 device.
If the I2WID bit is set to 1, the I
2
C interrupt
service routine can be terminated and there
won’t be another I
2
C Rx available interrupt until
the next I
2
C transaction.
If the I2WID bit is cleared, the RX Available
interrupt, if enabled, will be triggered for each
data byte received.
I
2
C Clock Speed
The VMX51C1020’s I
2
C communication speed is
fully configurable.
Control of the I
2
C communication speed enabled
via the I2CCLKCTRL register. The following
2
1
0
I2CWID
Function
0
I2WID
formula is used to calculate the I
2
C clock
frequency in Master mode.
I
2
C Clk = ________f
osc
__________
[8 x (I2CCLKCTRL)]
The following table provides examples of I
2
C
clock (on SCL pin) speeds for various setting of
the I2CCLKCTRL register when using a
14.75MHz oscillator to drive the VMX51C1020.
I2CCLKCTRL Value
01h
03h
07h
13h
27h
C7h
When the I
2
C interface is configured for slave
modethe I2CCLKCTRL is not used
T
ABLE
90:
(I2CCLKCTRL)
I2C
C
LOCK
C
ONTROL
-
SFR
DB
H
7
6
5
4
I2CCLKCTRL [7:0]
Bit
Mnemonic
Function
7:0
I2CCLKCTRL
I2C Clock speed control
I2C Clock (SCL Value)
920kHz
461KHz
230KHz
92KHz
46KHz
9.2KHz
3
2
1
0
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