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| 型號： | VMX1C1020 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Versa Mix 8051 Mixed-Signal MCU |
| 中文描述： | 反之亦然混合8051混合信號微控制器 |
| 文件頁數(shù)： | 29/80頁 |
| 文件大?。?/td> | 3605K |
| 代理商： | VMX1C1020 |
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VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 29 of 80
Timer2
The VMX51C1020 Timer2 and associated
peripherals include the following capabilities:
o
o
o
o
16-Bit Timer
16-Bit Auto-Reload Timer
Compare and Capture units
8 / 16 PWM outputs
T
ABLE
46:
(TL2)
T
IMER
2,
L
OW
B
YTE
-
SFR
CC
H
7
6
5
4
TL2 [7:0]
3
2
1
0
T
ABLE
47:
(TH2)
T
IMER
2,
H
IGH
B
YTE
-
SFR
CD
H
7
6
5
4
TH2 [7:0]
3
2
1
0
Figure 21 shows the Timer2 Compare/Capture
unit block diagram. The following paragraphs
will describe describe how these blocks work.
Timer2 Registers
Timer2 constists of a 16-bit register, whose
upper and lower bytes are accessible via two
independent SFR registers (TL2, TH2).
T
ABLE
48:
(TL2)
T
IMER
2
L
OW
B
YTE
-
SFR
CC
H
7
6
5
4
TL2 [7:0]
T
ABLE
49:
(TH2)
T
IMER
2
H
IGH
B
YTE
-
SFR
CD
H
7
6
5
4
TH2 [7:0]
3
2
1
0
3
2
1
0
Timer2 Control Register
Most of Timer2’s control is accomplished via the
T2CON register located at SFR address C8h.
The T2CON register controls:
o
T2 clock source Prescaler
o
T2 count size (8/16-bits)
o
T2 reload mode
o
T2 Input selection
T
ABLE
50:
(T2CON)
T
IMER
2
C
ONTROL
R
EGISTER
-SFR
C8
H
7
6
T2PS
T2PSM
5
4
T2SIZE
T2RM1
3
2
1
0
T2RM0
T2CM
T2IN1
T2IN0
Bit
7
Mnemonic
T2PS
Function
Prescaler select bit:
0 = Timer 2 is clocked with 1/12 of
the oscillatory frequency
1 = Timer 2 is clocked with 1/24 of
the oscillatory frequency
0 = Prescaler
1 = clock/2
Timer 2 Size
0 = 16-bit
1 = 8-bit
Timer 2 reload mode selection
0X = Reload disabled
10 = Mode 0
11 = Mode 1
Timer 2 compare mode selection
0 = Mode 0
1 = Mode 1
Timer 2 input selection
00 = Timer 2 stops
01 = Input frequency f/2, f/12 or f/24
10 = Timer 2 is incremented by
external signal at pin T2IN
11 = Internal clock is gated to the
T2IN input.
6
T2PSM
5
T2SIZE
4
3
T2RM1
T2RM0
2
T2CM
1
0
T2IN1
T2IN0
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