參數(shù)資料
型號: VMX1C1020
廠商: Electronic Theatre Controls, Inc.
英文描述: Versa Mix 8051 Mixed-Signal MCU
中文描述: 反之亦然混合8051混合信號微控制器
文件頁數(shù): 74/80頁
文件大小: 3605K
代理商: VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 74 of 80
Power-on/Brown-Out Reset
The VMX51C1020 includes a Power-On-
Reset/Brown-Out detector circuit that ensures
the VMX51C1020 enters and stays in the reset
state as long as the supply voltage is below the
reset threshold voltage (order of 3.7 – 4.0 Volts).
In most applications, the VMX51C1020 requires
no external components to perform a Power-on
Reset when the device is powered on.
The VMX51C1020 includes a RESET input for
applications in which external Reset control is
required. The reset pin includes an internal pull-
up resistor. When a Power-on reset occurs, all
SFR locations return to their default values and
peripherals are disabled.
Errata Note:
The VMX51C1020 may fail to exit the reset state if the
supply voltage drops below the reset threshold, but
not below 3V. For applications where this condition
can occur, use an external supply monitoring circuit to
reset the device.
Processor Power Control
The processor power management unit has two
modes of operation: IDLE and STOP mode.
IDLE Mode
When the VMX51C1020 is in IDLE mode, the
processor clock is halted. However, the internal
clock and peripherals continue to run. The
power consumption drops because the CPU is
not active. As soon as an interrupt or reset
occurs, the CPU exits the IDLE mode.
In order to enter IDLE mode, the user must set
the IDLE bit of the PCON register. Any enabled
interrupts will force the processor to exit IDLE
mode
STOP Mode
In this mode, in contrast to IDLE mode, all
internal clocking shuts down. In order to enter
STOP mode, the user must set the STOP bit of
the PCON register. The CPU will exit this state
only when a non-clocked external interrupt or
reset occurs (internal interrupts are not possible
because they require clocking activity).
The
following
interrupts
processor from STOP mode: Reset, INT0, INT1,
SPI Rx/Rx Overrun, and the I
2
C interface.
F
IGURE
46:
P
OWER
M
ANAGEMENT ON THE
VMX51C1020
IDLE
can
restart
the
CLKCPU
GATE
CLKPER
GATE
STOP
INTERRUPT
REQUEST
CLK
CLK FOR
CPU
CLK FOR
PERIPHERALS
The following table describes the power control
register of the VMX51C1020.
T
ABLE
126:
(PCON)
P
OWER
C
ONTROL
(CPU)
-
SFR
87
H
7
6
5
4
3
SMOD
-
-
-
GF1
Bit
Mnemonic
Function
7
SMOD
The speed in Mode 2 of Serial Port 0
is controlled by this bit. When
SMOD= 1, f
/32. This bit is also
significant in Mode 1 and 3, as it
adds a factor of 2 to the baud rate.
6
-
-
5
-
-
4
-
-
3
GF1
Not used for power management
2
GF0
Not used for power management
1
STOP
Stop mode control bit. Setting this bit
turns on the STOP Mode. STOP bit
is always read as 0.
0
IDLE
IDLE mode control bit. Setting this bit
turns on the IDLE mode. IDLE bit is
always read as 0.
2
1
0
GF0
STOP
IDLE
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