參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁(yè)數(shù)： 14/80頁(yè)
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
Input Voltage vs. Ext. device sink
_________________________________________________________________________________________________
www.ramtron.com
page 14 of 80
The I/Os of the VMIX, when configured as
Inputs, include an internal pull-up resistor made
of a transistor that ensures the level present at
the input is stable when the I/O pin is
unconnected.
Due to the presence of the pull-up resistor on
the digital inputs, the external device driving the
I/O must be able to sink enough current to bring
the I/O pin low.
The following figure shows the VMX51C1020
Input port voltage vs. external device sink
current.
F
IGURE
13:
I
NPUT PORT
V
OLTAGE VS
.
EXT DEVICE SINK CURRENT
5.0
I
Ext. device sink current (uA)
0.0
1.0
2.0
3.0
4.0
0
20
40
60
80
100
120
140
160
180
I/O Port Configuration Registers
The VMX51C1020’s I/O port operation is
controlled by two sets of four registers which
are:
o
The Port Pin Configuration registers
o
The Port Access registers
The port pin configuration registers combined
with specific peripheral configuration will define if
a given pin acts as a general purpose I/O or if it
provides alternate peripheral functionality.
Before using a peripheral that is shared with
I/Os, the pin corresponding to the peripheral
output must be configured as an output and the
pins that are shared with the peripheral inputs
must be configured as inputs.
The following registers are used to configure
each of the ports as either general-purpose
input, output or alternate peripheral function..
For example, when bit 5 of Port 2 is configured
as an output, it will output the SCK signal if the
SPI interface is enabled and working.
The only exception to this rule is the I
2
C Clock
and data bus signals. In these two cases, the
VMX51C1020 configures the pins automatically
as inputs or outputs.
The P0PINCFG register controls the I/O access
to UART1, the Timer 2 input and output, as well
as defines the direction of the P0 when used as
general purpose I/O.
T
ABLE
15:
(P0PINCFG)
P
ORT
0
P
ORT
C
ONFIGURATION
R
EGISTER
-
SFR
9B
H
7
6
P07IO
P06IO
3
2
P0.3/RX1INE
P0.2/TX1OE
Bit
Mnemonic
Function
7:4
P0xIO
Unavailable on VMX51C1020
3
P0.3/RX1INE
0: General purpose input or
UART1 RX
1: General purpose output
When using UART1 you must
set this bit to 0.
2
P0.2/TX1OE
0: General purpose input
1: General purpose output or
UART1 TX
When using UART1 you must
set this bit to 1.
1
P0.1/T2EXINE
0: General purpose input or
Timer 2 EX
1: General purpose output
When using Timer 2EX input
you must set this bit to 0.
0
P0.0/T2INE
0: General purpose input or
Timer 2 IN
1: General purpose output
When using Timer 2 input
you must set this bit to 0.
5
4
P05IO
P04IO
1
0
P0.1/T2EXINE
P0.0/T2INE
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