參數(shù)資料
型號(hào)： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號(hào)微控制器
文件頁(yè)數(shù)： 73/80頁(yè)
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 73 of 80
The Clock Control Circuit
The VMX51C1020’s clock control circuit allows
dynamic adjustment of the clock from which the
processor and the peripherals derive their clock
source. This allows reduction of overall power
consumption by modulating the operating
frequency according to processing requirements
or peripheral use.
A typical application for this can be portable
acquisition systems in which significant power
savings can be achieved by lowering the
operating frequency between A/D conversions
and automatically throttling it back to full speed
when an A/D interrupt is generated. Note that
A/D converter operation is not affected by the
Clock Control Unit.
The clock control circuit allows adjusting the
System clock from [Fosc/1] (full speed) down to
[Fosc/512]. The clock division control is done
via the CLKDIVCTRL register located at address
94h of the SFR register area.
T
ABLE
125:
(CLKDIVCTRL)
C
LOCK
D
IVISION
C
ONTROL
R
EGISTER
-SFR
94
H
7
6
SOFTRST
-
3
2
MCKDIV [3:0]
Bit
Mnemonic
Function
Writing 1 into this bit location
provokes a reset. Read as a 0
6:5
-
0 = Full Speed in IRQ
1 = Selected speed during
IRQs
Master Clock Divisor
0000 – Sys CLK
0001 = SYS /2
0010 = SYS /4
0011 = SYS /8
0100 = SYS /16
0101 = SYS /32
0110 = SYS /64
0111 = SYS /128
1000 = SYS /256
1001 = SYS /512
(…)
1111 = SYS /512
The value written into the lower nibble of the
CLKDIVCTRL register, MCKDIV[3:0], defines
the clock division ratio.
When the IRQNORMSPD bit is cleared, the
VMX51C1020 will run at the maximum operating
speed when an interrupt occurs (see following
figure).
5
-
4
IRQNORMSPD
1
0
7
SOFTRST
-
4
IRQNORMSPD
3:0
MCKDIV [3:0]
F
IGURE
45:
C
LOCK
T
IMING
W
HEN AN
I
NTERRUPT
O
CCURS
INTERNAL
CLOCK
INTERRUPT
INTERRUPT
CLEARED
INTERRUPT
SET
Once the interrupt is cleared, the VMX51C1020
returns to the selected operating speed as
defined by the MCKDIV [3:0] bits of the
CLKDIVCTRL register.
When the IRQNORMSPD bit is set, the
VMX51C1020 will continue to operate at the
selected speed as defined by the MCKDIV [3:0]
bits of the CLKDIVCTRL register.
Note:
With the exception of the A/D converter
and analog only peripherals such as the
current source, potentiometers and op-
amp, all the peripheral operating speeds
are affected by the Clock Control circuit
Software Reset
Software reset can be generated by setting the
SOFTRST bit of the CLKDIVCTRL register to 1.
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