參數(shù)資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數(shù)： 12/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
Peripheral Activation Control
_________________________________________________________________________________________________
www.ramtron.com
page 12 of 80
Digital Peripheral Power Enable
In order to save power upon reset, many of the
digital peripherals of the VMX51C1020 are not
activated. The peripherals affected by this
feature are:
o
Timer 2 / Port1
o
Watchdog Timer
o
MULT/ACCU unit
o
I2C interface
o
SPI interface
o
UART0
o
UART1
o
Differential Transceiver
Before using any of the above-listed peripherals,
they must first be enabled by setting the
corresponding bit of the DIGPWREN SFR
register to 1.
The same rule applies when accessing a given
peripheral’s SFR register(s). The targeted
peripheral must have been powered on
(enabled) first, otherwise the SFR register
content will be ignored
The following table shows the structure of the
DIGPWREN register.
T
ABLE
13:
(DIGPWREN)
D
IGITAL
P
ERIPHERALS
P
OWER
E
NABLE
R
EGISTER
-
SFR
93
H
7
6
T2CLKEN
WDOGEN
3
2
SPIEN
UART1DIFFEN
Bit
Mnemonic
Function
Timer 2 / PWM Enable
0 = Timer 2 CLK stopped
1 = Timer 2 CLK Running
Watchdog Enable
0 = Watchdog Disable
1 = Watchdog Enable
1 = MULT/ACCU Unit Enable
0 = MULT/ACCU Unit Disable
1= I2C Interface Enable
0 = I2C Interface Disable
This bit is merged with CLK STOP bit
1 = SPI interface is Enable
0 = SPI interface is Disable
UART1 Differential mode
0 = Disable
1 = Enable
0 = UART1 Disable
1 = UART1 Enable
0 = UART0 Disable
1 = UART0 Enable
5
4
MACEN
I2CEN
1
0
UART1EN
UART0EN
7
T2CLKEN
6
WDOGEN
5
MACEN
4
I2CEN
3
SPIEN
2
UART1DIFFEN
1
UART1EN
0
UART0EN
Analog Peripheral Power Enable
The analog peripherals, specifically, the op-amp
digital potentiometer, current source and analog
to digital converter, have a shared dedicated
register used for enabling and disabling these
peripherals. By default, these peripherals are
powered down when the device is reset.
T
ABLE
14:
(ANALOGPWREN)
A
NALOG
P
ERIPHERALS
P
OWER
E
NABLE
R
EGISTER
-
SFR
92
H
7
6
OPAMPEN
DIGPOTEN
3
2
TAEN
ADCEN
PGAEN
Bit
Mnemonic
Function
1 = User Op-Amp Enable
0 = User Op-Amp Disable
1 = Digital Potentiometer and
Switch Enable
0 = Digital Potentiometer and
Switch Disable
0 = ISRC with 200mV feedback
1 = ISRC with 200mV feedback
1 = ISRC Output Enable
0 = ISRC Output Disable
1 = TA Output Enable
0 = TA Output Disable
1 = ADC Enable
0 = ADC Disable
1 = PGA Enable
0 = PGA Disable
1 = Bandgap Enable
0 = Bandgap Disable
Note
: The SFR registers associated with all
analog peripherals are activated when
one or more analog peripherals are
enabled.
5
4
ISRCSEL
ISRCEN
1
0
BGAPEN
7
OPAMPEN
6
DIGPOTEN
5
ISRCSEL
4
ISRCEN
3
TAEN
2
ADCEN
1
PGAEN
0
BGAPEN
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