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參數(shù)資料
| 型號： | VMX1C1020 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Versa Mix 8051 Mixed-Signal MCU |
| 中文描述： | 反之亦然混合8051混合信號微控制器 |
| 文件頁數(shù)： | 18/80頁 |
| 文件大?。?/td> | 3605K |
| 代理商： | VMX1C1020 |
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VMX51C1020
MULT/ACCU - Multiply
Accumulator Unit
_________________________________________________________________________________________________
www.ramtron.com
page 18 of 80
The VMX51C1020 includes a hardware based
multiply-accumulator unit which provides the
user the ability to perform fast and complex
arithmetic operations.
MULT/ACCU Features:
o
Hardware Calculation Engine
o
Calculation result is ready as soon as
the input registers are loaded
o
Signed mathematical calculations
o
Unsigned MATH operations are possible
if the MUL engine operands are limited
to 15-bits in size
o
Auto/Manual reload of MAC_RES
o
Enhanced VMX51C1020 MULT/ACCU
Unit
o
Easy implementation of complex MATH
operations
o
16-bit and 32-bit Overflow Flag
o
32-bit Overflow can raise an interrupt
o
MULT/ACCU operand registers can be
cleared individually or all together
o
Overflow flags can be configured to stay
active until manually cleared
o
Can store and use results from previous
operations
The MULT/ACCU can be configured to perform
the following operations:
F
IGURE
13:
VMX51C1020
MULT/ACCU
O
PERATION
(MACA x MACB) + MACC = MAC_RESULT
(MACA x MACB) + 0
(MACA x MACB) + MAC_PREV
= MAC_RESULT
= MAC_RESULT
(MACA x MACA) + MACC = MAC_RESULT
(MACA x MACA) + 0
(MACA x MACA) + MAC_PREV
= MAC_RESULT
= MAC_RESULT
(MACA x MAC_PREV(16lsb) + MACC
(MACA x MAC_PREV(16lsb) + 0
(MACA x MAC_PREV(16lsb) + MAC_PREV = MAC_RESULT
= MAC_RESULT
= MAC_RESULT
ADD32 + ADD32
MULT16 + ADD32
(MACA, MACB) + MACC = MAC_RESULT
Where MACA (multiplier), MACB (multiplicand),
MACACC (accumulator) and MACRESULT
(result) are 16, 16, 32 and 32 bits, respectively.
MULT/ACCU Control Registers
With the exception of the Barrel Shifter, the
MULT/ACCU unit operation is controlled by two
SFR registers:
o
The MACCTRL1
o
The MACCTRL2
The following two tables describe the details of
these control registers.
T
ABLE
20:
(MACCTRL1)
MULT/ACCU
U
NIT
C
ONTROL
R
EGISTER
-
SFR
EB
H
7
6
LOADPREV
PREVMODE
3
2
ADDSRC [1:0]
Bit
Mnemonic
Function
7
LOADPREV
MACPREV manual Load control
1 = Manual load of the
MACPREV register content if
PREVMODE = 1
6
PREVMODE
Loading method of MACPREV
register
0 = Automatic load when
MACA0 is written.
1 = Manual Load when 1 is
written into LOADPREV
5
OVMODE
0 = Once set by math operation,
the OV16 and OV32 flag will
remain set until the overflow
condition is removed.
1= Once set by math operation,
the OV16 and OV32 flag will
stay set until it is cleared
manually.
4
OVRDVAL
0 = The value on MACRES is
the calculation result.
1 = the value on MACRES is the
32LSB of the MACRES when
the OV32 overflow occurred
3:2
ADDSRC[1:0]
32-bit Addition source
B Input
00 = 0 (No Add)
01 = C (std 32-bit reg)
10 = RES –1
11 = C (std 32-bit reg)
A Input
00=Multiplication
01=Multiplication
10=Multiplication
11= Concatenation of {A, B} for
32-bit addition
1:0
MULCMD[1:0]
Multiplication Command
00 = MACA x MACB
01 = MACA x MACA
10 = MACA x MACPREV
(16 LSB)
11 = MACA x MACB
5
4
OVMODE
OVRDVAL
1
MULCMD [1:0]
0
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