參數資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數： 26/80頁
文件大小： 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 26 of 80
Timer0, Timer1 Operation Modes
The operating mode of Timer0 and Timer1 is
determined by the M1x and M0x bits in the
TMOD register. The following summarizes the
four modes of operation for Timers0 and 1.
T
ABLE
45:
T
IMER
/C
OUNTER
M
ODE
D
ESCRIPTION
S
UMMARY
M1
M0
Mode
0
0
Mode 0
Function
13-bit Timer / Counter
, with 5
lower bits in TL0 or TL1 register
and bits in TH0 or TH1 register
(for timer 0 and timer 1,
respectively). The 3 high order
bits of TL0 and TL1 are held at
0.
16-bit Timer / Counter
8-bit auto reload Timer /
Counter
. The reload value is
kept in TH0 or TH1, while TL0
or TL1 is incremented every
machine cycle. When TLx
overflows, a value from THx is
copied to TLx.
If Timer 1 M1 and M0 bits are
set to 1, Timer 1 stops. If Timer
0 M1 and M0 bits are set to 1,
Timer
0
acts
independent
8-bit
Counters.
0
1
1
0
Mode 1
Mode 2
1
1
Mode 3
as
Timers
two
/
Mode 0, 13-bit Timer/Counter
Mode 0 operation is the same for Timer0 and
Timer1.
In Mode 0, the timer is configured as a 13-bit
counter that uses bits 0-4 of the TLx register and
all 8-bits of the THx register. The Timer Run bit
(TRx) of the TCON SFR starts the timer. The
value of the CTx bit defines if the Timer will
operate as a Timer (CTx = 0), deriving its source
from the System Clock, or count the High to Low
Transitions (CTx = 1) that occurs on the External
Timer input pin (TxIN). When the 13-bit count
increments from 1FFFh (all ones) to all zeros,
the TF0 (or TF1) bit will be set in the TCON
SFR.
The state of the upper 3-bits of the TLx register
is indeterminate in Mode 0 and must be masked
when the software evaluates the register’s
contents.
Timer 0, Timer 1: Mode 0 - Overflow Rate (Hz)
CTx = 0
Timer overflow rate (Hz) = f
SYSCLK
_________
12 x [8192-(THx, TLx)]
CTx = 1
Timer overflow rate (Hz) = f
_________
[8192-(THx,TLx)]
Mode 1 (16-bit)
Mode 1 operation is the same for Timer0 and
Timer1. In Mode 1, the timer is configured as a
16-bit counter. Other than rollover at FFFFh,
Mode 1 operation is the same as Mode 0.
F
IGURE
16 :
T
IMER
0
M
ODE
0
&
M
ODE
1
SYSCLK
÷12
P3.2-T0IN
CT0=0
CT0=1
TR0
GATE0
INT0
0
1
0
7
4
Mode = 0
0
7
TH0
TF0
INT
TL0
CLK
Mode = 1
F
IGURE
17:
T
IMER
1
M
ODE
0
&
M
ODE
1
SYSCLK
÷12
P3.5-T1IN
CT1=0
CT1=1
TR1
GATE1
INT1
0
1
0
7
4
Mode = 0
TH1
CLK
Mode = 1
0
7
TF1
INT
TL1
To UART0
The Timer0 and Timer1 overflow rate in mode 1
can be calculated using the following equations:
Timer 0, Timer 1: Mode 1 - Overflow Rate (Hz)
CTx = 0
Timer overflow rate (Hz) = f
_________
12 x [65536-(THx, TLx)]
CTx = 1
Timer overflow rate (Hz) = f
_________
[65536-(THx, TLx)]
Mode 2 (8-bit)
The operation of Mode2 is the same for Timer0
and Timer1. In Mode 2, the timer is configured
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