參數(shù)資料
型號(hào): VMX1C1020
廠商: Electronic Theatre Controls, Inc.
英文描述: Versa Mix 8051 Mixed-Signal MCU
中文描述: 反之亦然混合8051混合信號(hào)微控制器
文件頁數(shù): 69/80頁
文件大?。?/td> 3605K
代理商: VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 69 of 80
The respective values of the IP1.x and IP0.x bits
define the priority level of the interrupt group vs.
the other interrupt groups as follows.
T
ABLE
121:
I
NTERRUPT
P
RIORITY
L
EVEL
IP1.x
IP0.x
0
0
0
1
1
0
1
1
The WDTSTAT bit of the IP0 register is the
Watchdog status flag and is set to 1 by the
hardware whenever a Watchdog Timer overflow
occurs. This bit must be cleared manually.
Finally, bit 7 of the IP0 register can be used as a
general purpose user flag.
Priority Level
Level 0 (Low)
Level 1
Level 2
Level 3 (High)
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