參數(shù)資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數(shù)： 25/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 25 of 80
The TMOD register is mainly used to set the
operating mode of the timers and it allows the
user to enable the external gate control as well
as select timer or counter operation.
T
ABLE
44:
(TMOD)
T
IMER
M
ODE
C
ONTROL
-
SFR
89
H
7
6
GATE1
CT1
3
2
GATE0
CT0
Bit
Mnemonic
Function
7
GATE1
GATE1 = 0,
The level present on the INT1 pin has
no effect on Timer1 operation.
GATE1 = 1,
The level of INT1 pin serves as a Gate
control on to Timer/Counter operation
provided the TR1 bit is set. Applying a
Low Level on the INT1 pin makes the
Timer stop.
CT1
Selects TIMER1 Operation.
CT1 = 0,
CT1 = 1, The Timer 1 operates as a
5
M11
4
M01
shown in the Table below.
3
GATE0
GATE0 = 0,
The level present on the INT0 pin has
no effect on Timer1 operation.
GATE0 = 1,
The level of INT0 pin serves as a Gate
control on to Timer/Counter operation
provided the TR0 bit is set. Applying a
Low Level on the INT0 pin makes the
Timer stop.
2
CT0
Selects Timer 0 Operation.
CT1 = 0,
CT1 = 1, The Timer 0 operates as a
1
M10
0
M00
shown in the Table below.
Timer0/Timer1/Counter Operation
5
4
M11
M01
1
0
M10
M00
Sets the Timer 1 as a Timer
which value is incremented
by SYSCLK events.
counter which counts the
High to Low transition on
that occurs on the T1IN
input.
Selects mode for Timer/Counter 1, as
Sets the Timer 0 as a Timer
which value is incremented
by SYSCLK events.
counter which counts the
High to Low transition on
that occurs on the T1IN
input.
Selects mode for Timer/Counter 0, as
The CT0 and CT1 bits of the TMOD register
control the Clock source for Timer0 and Timer1,
respectively. When the CT bit is set to 0 (Timer
mode) the Timer is sourced from the system
clock divided by 12.
Setting the CTx bit to 1 sets the Timer to operate
in event counter mode. In this mode, High to
Low transitions on the TxIN pin of the
VMX51C1020 increments the timer value.
Note that when Timer0 and Timer1 operate in
Timer mode, they use the System Clock as their
source. Therefore configuring the CLKDIVCTRL
register will affect the Timer’s operation.
Timer0 & Timer1 Gate Control
The Gate control makes it possible for an
external device to control Timer0 and Timer1
operation through the interrupt (INTx) pins.
When the GATEx and TRx bits of the TMOD
register are set to 1:
o
INTx = Logic LOW, The Timer x Stops
o
INTx = Logic High, The Timer x Runs
When the Gate bit equals 0, then the logic level
present at the INTx pin have no effect on the
Timer Operation.
F
IGURE
15:
T
IMER
0,
T
IMER
1
CT
X
&
G
ATE CONTROL
SYSCLK
÷12
TxIN
CTx=0
CTx=1
TRx
GATEx
INTx
0
1
CLK
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