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參數(shù)資料
| 型號： | VMX1C1020 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Versa Mix 8051 Mixed-Signal MCU |
| 中文描述： | 反之亦然混合8051混合信號微控制器 |
| 文件頁數(shù)： | 47/80頁 |
| 文件大?。?/td> | 3605K |
| 代理商： | VMX1C1020 |
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VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 47 of 80
SPI Operating Speed
Three bit in the SPICTRL register serve to adjust
the communication speed of the SPI interface.
SPICK[2:0]
Div Ratio
14.74MHz
Clk Div 2
7.37 MHz
Clk Div 4
3.68 MHz
Clk Div 8
1.84 MHz
Clk Div 16
922 kHz
Clk Div 32
461 kHz
Clk Div 64
230 kHz
Clk Div 128
115 kHz
Clk Div 256
57.6 kHz
SPI Master Chip Select Control
Fosc =
Fosc =
11.059MHz
5.53 MHz
2.76 MHz
1.38 MHz
691 kHz
346 kHz
173 kHz
86 kHz
43.2 kHz
When the SPI is configured in Master mode, the
value of the SPICS[1:0] bits will define which
Chip select pins will be active during the
transaction.
The following sections will describe how the SPI
Clock Polarity and Phase affects the read and
write operations of the SPI interface.
SPI Operating Modes
The SPI interface can operate in four distinct
modes defined by the SPICKPH and SPICKPOL
bits of the SPICTRL register.
SPICKPH defines the SPI clock phase and
SPICKPOL defines the Clock polarity for data
exchange.
SPICKPOL
bit value
bit value
0
0
0
1
1
0
1
1
SPI Mode 0
SPICKPH
SPI Operating Mode
SPI Mode 0
SPI Mode 1
SPI Mode 2
SPI Mode 3
o
Data is placed on the SDO pin at the
rising edge of the clock.
Data is sampled on the SDI pin at the
falling edge of the clock.
o
F
IGURE
31 :
SPI
M
ODE
0
MSB
LSB
CS
X
SCK
SDI
SDO
SPI MODE 0: SPICKPOL =0,SPICKPH =0
*Arrows indicate the edge where the data acquisition occurs
SPI Mode 1
o
Data is placed on the SDO pin at the
falling edge of the clock.
Data is sampled on the SDI pin at the
rising edge of the clock.
o
F
IGURE
32:
SPI
M
ODE
1
SPI MODE 1: SPICKPOL =0,SPICKPH =1
CS
X
SCK
SDI
SDO
MSB
LSB
*Arrows indicate the edge where the data acquisition occurs
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