參數(shù)資料
型號： VMX1C1020
廠商： Electronic Theatre Controls, Inc.
英文描述： Versa Mix 8051 Mixed-Signal MCU
中文描述： 反之亦然混合8051混合信號微控制器
文件頁數(shù)： 51/80頁
文件大?。?/td> 3605K
代理商： VMX1C1020
VMX51C1020
_________________________________________________________________________________________________
www.ramtron.com
page 51 of 80
SPI Interrupt Example
The following provides an example of basic SPI
configuration and Interrupt handling.
//-------------------------------------------------------------------------------//
// Sample C code for SPI RX & TX interrupt set-up
//-------------------------------------------------------------------------------//
//
#pragma SMALL
#include <vmixreg.h>
at 0x0100 main (void) {
DIGPWREN = 0x08;
// Enable SPI
P2PINCFG = 0x4F;
// Set pads direction
SPICONFIG = 0x03;
// Enable Rx_avail + TX_empty
SPISIZE = 0x07;
// SPI SIZE: 8 bits
IEN0 |= 0x80;
// Enable all interrupts
IEN1 |= 0x06;
// Enable SPI Txempty + RXavail interrupt
SPIRX3TX0 = valhigh;
//Put MSB of value in SPI transmit buffer
//-> trigger transmission
Do{
}while(1)
}//end of main()
//---------------------------------------------------------------------------//
// SPI TX Empty Interrupt function
//---------------------------------------------------------------------------//
void int_2_spi_tx (void) interrupt 9
{
IEN0 &= 0x7F;
// Disable all interrupts
/*-------------------------*/
/* Interrupt code here*/
/*-------------------------*/
IRCON &= 0xFD;
// Clear flag SPITXIF
IEN0 |= 0x80;
// Enable all interrupts
}
//---------------------------------------------------------------------------//
// SPI RX availlable function
//---------------------------------------------------------------------------//
void int_2_spi_rx (void) interrupt 10
{
IEN0 &= 0x7F;
// Disable all interrupts
/*-------------------------*/
/* Interrupt code here*/
/*-------------------------*/
IRCON &= 0xFB;
// Clear flag SPIRXIF
IEN0 |= 0x80;
// Enable all interrupts
}
//---------------------------------------------------------------------------//
Due to the double buffering of the SPI interface,
an SPI TX empty interrupt will be activated as
soon as the data to be transmitted is written into
the SPI interface transmit buffer. If data is
subsequently written into the SPI transmit buffer
before the original data has been transmitted,
the TX empty interrupt will only be activated
when the original data has been fully
transmitted.
The SPI also includes double buffering for data
reception. Once a data reception is completed,
the RX interrupt is activated and the data is
transferred into the SPI RX buffer. At this point,
the SPI interface can receive more data.
However, the processor must have retrieved the
first data stream before the second data stream
reception is complete, otherwise a data overrun
will occur and the SPI RX overrun interrupt will
be activated, if enabled.
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