參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁(yè)數(shù)： 99/133頁(yè)
文件大小： 883K
代理商： PLI9080
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SECTION 5
PCI 9080
PIN DESCRIPTION
PLX Technology, Inc., 1997
Page 91
Version 0.93
Table 5-6. J Bus Mode Interface Pin Description (continued)
J Mode Bus
Symbol
Signal Name
Total
Pins
Pin
Type
Pin
Number
Function
LBE[3:0]#
Byte Enables
4
I/O
TS
12 mA
139-142
The byte enables are encoded based on configured bus width as follows:
32-Bit Bus:
For a 32-bit bus, the four byte enables indicate which of the four bytes
are active during a data cycle:
BE3# Byte Enable 3—LAD[31:24]
BE2# Byte Enable 2—LAD[23:16]
BE1# Byte Enable 1—LAD[15:8]
BE0# Byte Enable 0—LAD[7:0]
16-Bit Bus:
For a 16-bit bus, BE3#, BE1# and BE0# are encoded to provide BHE#,
A1 and BLE#, respectively:
BE3# Byte High Enable (BHE#)—LAD[15:8]
BE2# not used
BE1# Address bit 1 (A1)
BE0# Byte Low Enable (BLE#)—LAD[7:0]
8-Bit Bus:
For an 8-bit bus, BE1# and BE0# are encoded to provide A1and A0,
respectively:
BE3# not used
BE2# not used
BE1# Address bit 1 (A1)
BE0# Address bit 0 (A0)
LCLK
System Clock
1
I
160
Local clock input.
LHOLD
Hold Request
1
O
TP
8 mA
158
Asserted to request use of the local bus. The local bus arbiter asserts
LHOLDA when control is granted.
LHOLDA
Hold Acknowledge
1
I
159
Asserted by the local bus arbiter when control is granted in response to
LHOLD. The bus should not be granted to the PCI 9080 unless
requested by LHOLD.
LLOCK#
Bus Lock
1
I
153
Indicates an atomic operation that may require multiple transactions to
complete. Used by the PCI 9080 for direct local access to the PCI bus.
LRESETo#
Local Bus Reset Out
1
O
TP
8 mA
11
Asserted when the PCI 9080 chip is reset.
READYi#
Ready In
1
I
147
When the PCI 9080 is a bus master, READYi# is used to indicate read
data on the bus is valid or a write data transfer is complete. READYi# is
used in conjunction with the PCI 9080 programmable wait state
generator.
READYo#
Ready Out
1
O
DTS
8 mA
148
When a local bus access is made to the PCI 9080, indicates that read
data on the bus is valid or that a write data transfer is complete.
READYo# can be connected to READYi#.
EOT0#
End of Transfer for
DMA Ch 0
1
I
4
Terminates the current DMA Ch 0 transfer.
EOT1#
End of Transfer for
DMA Ch 1
1
I
5
Terminates the current DMA Ch 1 transfer.
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