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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 66/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 58
Version 0.93
4.4.3 (LARBR; PCI:08h or ACh, LOC:88h or 12Ch) Local/DMA Arbitration Register
Table 4-35. (LARBR; PCI:08h or ACh, LOC:88h or 12Ch) Local/DMA Arbitration Register
Field
Description
Read
Write
Value after Reset
7:0
Local Bus Latency Timer. Number of local bus clock cycles before negating HOLD and
releasing the local bus. This timer is also used with bit 27 to delay BREQ input to give
up the local bus only when this timer expires.
Yes
Yes
00
15:8
Local Bus Pause Timer. Number of local bus clock cycles before reasserting HOLD
after releasing the local bus.
Yes
Yes
00
16
Local Bus Latency Timer Enable. A value of 1 enables the latency timer.
Yes
Yes
0
17
Local Bus Pause Timer Enable. A value of 1 enables the pause timer.
Yes
Yes
0
18
Local Bus BREQ Enable. A value of 1 enables the local bus BREQ input. When the
BREQ input is active, the PCI 9080 negates HOLD and releases the local bus.
Yes
Yes
0
20:19
DMA Channel Priority. A value of 00 indicates a rotational priority scheme. A value
of 01 indicates Channel 0 has priority. A value of 10 indicates Channel 1 has priority. A
value of 11 is reserved.
Yes
Yes
0
21
Local Bus Direct Slave Give up Bus Mode. When set to 1, the PCI 9080 negates
HOLD and releases the local bus when the Direct Slave write FIFO becomes empty
during a Direct Slave write or when the Direct Slave read FIFO becomes full during a
Direct Slave read.
Yes
Yes
1
22
Direct Slave LLOCKo# Enable. A value of 1 enables PCI Direct Slave locked
sequences. A value of 0 disables Direct Slave locked sequences.
Yes
Yes
0
23
PCI Request Mode. A value of 1 causes the PCI 9080 to negate REQ when it asserts
FRAME during a master cycle. A value of 0 causes the PCI 9080 to leave REQ
asserted for the entire bus master cycle.
Yes
Yes
0
24
PCI Rev 2.1 Mode. When set to 1, the PCI 9080 operates in Delayed Transaction
mode for Direct Slave Reads. The PCI 9080 issues a RETRY and prefetches the read
data.
Yes
Yes
0
25
PCI Read No Write Mode. A value of 1 forces a retry on writes if read is pending.
A value of 0 allows writes to occur while read is pending.
Yes
Yes
0
26
PCI Read with Write Flush Mode. A value of 1 submits a request to flush a pending
read cycle if a write cycle is detected. A value of 0 submits a request to not effect
pending reads when a write cycle occurs (PCI 2.1 compatible).
Yes
Yes
0
27
Gate the Local Bus Latency Timer with BREQ. If this bit is set to 0, the PCI 9080 gives
up the local bus during Direct Slave or DMA transfer after the current cycle (if enabled
and BREQ is sampled). If this bit is set to 1, the PCI 9080 gives up the local bus only
(if enabled and BREQ is sampled) and the Local Bus Latency Timer is enabled and
expired during Direct Slave or DMA transfer.
Yes
Yes
0
28
PCI Read No Flush Mode. A value of 1 submits a request to not flush the read FIFO if
the PCI read cycle completes (cached read mode).
A value of 0 submits a request to flush the read FIFO if a PCI read cycle completes.
Yes
Yes
0
29
If set to 1, reads from the PCI Configuration Register address 00h return the Device ID
and Vendor ID. If set to 1, reads from the PCI Configuration Register address 00h
return the Subsystem ID and Subsystem Vendor ID.
Yes
Yes
0
31:30
Reserved.
Yes
No
0
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