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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 56/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 48
Version 0.93
4.3 PCI CONFIGURATION REGISTERS
All registers may be written to or read from in byte, word or long word accesses.
4.3.1 (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register
Table 4-10. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register
Field
Description
Read
Write
Value after Reset
15:0
Vendor ID. Identifies the manufacturer of the device. Defaults to the PCI SIG issued
vendor ID of PLX (10B5h) if no EEPROM is present and pin NB# (no local bus
initialization) is asserted low.
Yes
Local/
EEPROM
10B5h
or
0
31:16
Device ID. Identifies the particular device. Defaults to the PLX part number for
PCI interface chip (PCI 9080) if no EEPROM is present and pin NB# (no local bus
initialization) is asserted low.
Yes
Local/
EEPROM
9080h
or
0
4.3.1.1 (PCICR; PCI:04h, LOC:04h) PCI Command Register
Table 4-11. (PCICR; PCI:04h, LOC:04h) PCI Command Register
Field
Description
Read
Write
Value after Reset
0
I/O Space. A value of 1 allows the device to respond to I/O space accesses. A value
of 0 disables the device from responding to I/O space accesses.
Yes
Yes
0
1
Memory Space. A value of 1 allows the device to respond to memory space accesses.
A value of 0 disables the device from responding to memory space accesses.
Yes
Yes
0
2
Master Enable. A value of 1 allows the device to behave as a bus master. A value of 0
disables the device from generating bus master accesses.
Yes
Yes
0
3
Special Cycle. (This bit is not supported.)
Yes
No
0
4
Memory Write/Invalidate. (Refer to the DMA Mode Registers (DMAMODE0,
DMAMODE1) bit 13.
Yes
Yes
0
5
VGA Palette Snoop. (This bit is not supported.)
Yes
No
0
6
Parity Error Response. A value of 0 indicates a parity error is ignored and operation
continues. A value of 1 indicates parity checking is enabled.
Yes
Yes
0
7
Wait Cycle Control. Controls whether or not the device does address/data stepping. A
value of 0 indicates the device never does stepping. A value of 1 indicates the device
always does stepping.
Note: Hardcoded to 0.
Yes
No
0
8
SERR# Enable. A value of 1 enables the SERR# driver. A value of 0 disables the
driver.
Yes
Yes
0
9
Fast Back-to-Back Enable. Indicates what type of fast back-to-back transfers a Master
can perform on the bus. A value of 1 indicates fast back-to-back transfers can occur to
any agent on the bus. A value of 0 indicates fast back-to-back transfers can only occur
to the same agent as the previous cycle.
Yes
No
0
15:10
Reserved.
Yes
No
0
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