
TABLE OF CONTENTS
PLX Technology, Inc., 1997
Page vi
Version 0.93
4.4 LOCAL CONFIGURATION REGISTERS.............................................................................................................. 57
4.4.1 (LAS0RR; PCI:00h, LOC:80h) Local Address Space 0 Range Register for PCI to Local Bus .......................... 57
4.4.2 (LAS0BA; PCI:04h, LOC:84h) Local Address Space 0 Local Base Address (Remap) Register........................ 57
4.4.3 (LARBR; PCI:08h or ACh, LOC:88h or 12Ch) Local/DMA Arbitration Register ................................................ 58
4.4.4 (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register .............................................................. 59
4.4.5 (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Register................................................................... 60
4.4.6 (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) Register and BREQo Control 60
4.4.7 (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor Register.......... 61
4.4.8 (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for Direct Master to PCI .................................................. 62
4.4.9 (DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for Direct Master to PCI Memory............... 62
4.4.10 (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for Direct Master to PCI IO/CFG...................... 62
4.4.11 (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master to PCI Memory....... 63
4.4.12 (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for Direct Master to PCI IO/CFG......... 64
4.4.13 (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI to Local Bus ...................... 64
4.4.14 (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) Register ................... 65
4.4.15 (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Register................................ 65
4.5 RUNTIME REGISTERS........................................................................................................................................ 66
4.5.1 (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0 ................................................................................ 66
4.5.2 (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1................................................................................ 66
4.5.3 (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2........................................................................................... 66
4.5.4 (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3.......................................................................................... 66
4.5.5 (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4........................................................................................... 66
4.5.6 (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5........................................................................................... 67
4.5.7 (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6........................................................................................... 67
4.5.8 (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7.......................................................................................... 67
4.5.9 (P2LDBELL; PCI:60h, LOC:E0h) PCI to Local Doorbell Register..................................................................... 67
4.5.10 (L2PDBELL; PCI:64h, LOC:E4h) Local to PCI Doorbell Register................................................................... 67
4.5.11 (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status.................................................................................. 68
4.5.12 (CNTRL; PCI:6Ch, LOC:ECh) EEPROM Control, PCI Command Codes, User I/O Control,
Init Control Register................................................................................................................................................. 70
4.5.13 (PCIHIDR; PCI:70h, LOC:F0h) PCI Permanent Configuration ID Register..................................................... 71
4.5.14 (PCIHREV; PCI:74h, LOC:F4h) PCI Permanent Revision ID Register........................................................... 71
4.6 DMA REGISTERS................................................................................................................................................ 72
4.6.1 (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Register............................................................... 72
4.6.2 (DMAPADR0; PCI:84h, LOC:104h) DMA Channel 0 PCI Address Register..................................................... 73
4.6.3 (DMALADR0; PCI:88h, LOC:108h) DMA Channel 0 Local Address Register................................................... 73