參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁(yè)數(shù)： 61/133頁(yè)
文件大?。?/td> 883K
代理商： PLI9080
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 53
Version 0.93
4.3.11 (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to
Local Address Space 0
Table 4-21. (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address
Space 0
Field
Description
Read
Write
Value after
Reset
0
Memory Space Indicator. A value of 0 indicates the register maps into memory space.
A value of 1 indicates the register maps into I/O space.
(Specified in LAS0RR register.)
Yes
No
0
2:1
Location of Register (If memory space). Location values:
00—Locate anywhere in 32 bit memory address space
01—Locate below 1 MB memory address space
10—Locate anywhere in 64 bit memory address space
11—Reserved
(Specified in LAS0RR register.)
If I/O Space, bit 1 is always 0 and bit 2 is included in the base address.
Yes
Mem: No
I/O:
bit 1 no,
bit 2 yes
0
3
Prefetchable (If memory space). A value of 1 indicates there are no side effects on
reads. This bit reflects the value of bit 3 in the LAS0RR register and provides only
status to the system. This bit has no effect on the operation of the PCI 9080.
Prefetching features of this address space are controlled by the associated Bus
Region Descriptor Register.
(Specified in LAS0RR register.)
If I/O Space, bit 3 is included in the base address.
Yes
Mem: No
I/O: Yes
0
31:4
Memory Base Address. Memory base address for access to local address space 0.
Yes
Yes
0
Note: PCIBAR2 can be enabled or disabled by setting or clearing bit 0 in the LAS0BA register.
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