參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 4/133頁
文件大小： 883K
代理商： PLI9080
TABLE OF CONTENTS
PLX Technology, Inc., 1997
Page iv
Version 0.93
3.5.2.3 Direct Slave Lock......................................................................................................................................................22
3.5.3 Direct Slave Priority........................................................................................................................................ 22
3.6 DMA OPERATION................................................................................................................................................ 23
3.6.1 Non-Chaining Mode DMA............................................................................................................................... 23
3.6.2 Chaining Mode DMA....................................................................................................................................... 24
3.6.3 DMA Data Transfers....................................................................................................................................... 25
3.6.3.1 Local to PCI Bus DMA Transfer ................................................................................................................................25
3.6.3.2 PCI to Local Bus DMA Transfer ................................................................................................................................26
3.6.3.3 Unaligned Transfers..................................................................................................................................................26
3.6.4 Demand Mode DMA....................................................................................................................................... 26
3.6.5 DMA Priority................................................................................................................................................... 27
3.6.6 DMA Arbitration.............................................................................................................................................. 27
3.6.6.1 End of Transfer (EOT0# or EOT1#) Input..................................................................................................................27
3.6.6.2 Local Latency and Pause Timers ..............................................................................................................................27
3.7 BREQ INPUT........................................................................................................................................................ 27
3.8 DOORBELL REGISTERS..................................................................................................................................... 27
3.9 MAILBOX REGISTERS........................................................................................................................................ 27
3.10 INTERRUPTS..................................................................................................................................................... 28
3.10.1 PCI Interrupts (INTA#).................................................................................................................................. 28
3.10.1.1 Local Interrupt Input................................................................................................................................................28
3.10.1.2 Master/Target Abort Interrupt..................................................................................................................................28
3.10.2 Local Interrupts (LINTo#).............................................................................................................................. 29
3.10.2.1 Local to PCI Doorbell Interrupt................................................................................................................................29
3.10.2.2 PCI to Local Doorbell Interrupt................................................................................................................................29
3.10.2.3 Built In Self Test Interrupt (BIST).............................................................................................................................29
3.10.2.4 DMA Channel 0/1 Interrupts....................................................................................................................................29
3.10.3 PCI SERR# (PCI NMI).................................................................................................................................. 30
3.10.4 Local LSERR# (Local NMI)........................................................................................................................... 30
3.11 I
2
0 COMPATIBLE MESSAGE UNIT.................................................................................................................... 30
3.11.1 Inbound Messages ....................................................................................................................................... 30
3.11.2 Outbound Messages..................................................................................................................................... 31
3.11.3 I
2
O Pointer Management .............................................................................................................................. 31
3.11.4 Inbound Free List FIFO................................................................................................................................. 32
3.11.5 Inbound Post List FIFO................................................................................................................................. 34
3.11.6 Outbound Post List FIFO.............................................................................................................................. 34
3.11.7 Outbound Free List FIFO.............................................................................................................................. 34
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