參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁(yè)數(shù)： 15/133頁(yè)
文件大?。?/td> 883K
代理商： PLI9080
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SECTION 2
PCI 9080
BUS OPERATION
PLX Technology, Inc., 1997
Page 7
Version 0.93
2.2 LOCAL BUS CYCLES
The PCI 9080 connects a PCI host bus to several local
processor bus types:
32-bit nonmultiplexed (C mode)
32-bit multiplexed (J mode)
16-bit multiplexed (S mode)
The PCI 9080 operates in one of three modes, selected
through mode pins, corresponding to three bus types—
C, J, and S.
2.2.1 Local Bus Direct Master
Local bus cycles can be continuous single or burst
cycles (programmable by way of the PCI 9080 internal
registers). As a local bus target, the PCI 9080 allows
access to the PCI 9080 internal registers and the PCI
bus.
In C and J modes, local bus direct master accesses to
the PCI 9080 must be for a 32 bit non-pipelined bus. In
S mode, local bus direct master accesses to the PCI
9080 must be for a 16 bit non-pipelined bus.
2.2.2 Local Bus Direct Slave
The PCI Bus Master read/write to local bus (PCI 9080 is
a PCI bus target and local bus master).
2.2.2.1 Ready/Wait State Control
If the READY input is disabled, the external READY
input has no effect on wait states for a local access.
Wait states between data cycles are generated internally
by a wait state counter. The wait state counter is
initialized with its configuration register value at the start
of each data access.
If the READY input is enabled, the READY input has no
effect until the wait state counter is 0. The READY input
then controls the number of additional wait states.
The BTERM input is not sampled until the wait state
counter is 0.
2.2.2.2 Burst Mode and Continuous Burst
Mode (BTERM “Burst Terminate” Mode)
Note: BTERM refers to PCI 9080 internal register bit.
BTERM# refers to the PCI 9080 external signal.
2.2.2.2.1 Burst Mode
If Bursting is enabled and the BTERM input is not
enabled, bursting can start on any boundary and
continue up to an address boundary as described in
Table 2-6. After the data at the boundary is transferred,
the PCI 9080 generates a new address cycle (ADS#).
Table 2-6. Burst Mode
Bus Mode
Burst
C, J
32-bit bus—4 Lwords or up to a quad Lword
boundary (LA3, LA2 = 11)
C, J
16-bit bus—4 words or up to a quad word boundary
(LA2, LA1 = 11)
C, J
8-bit bus—4 bytes or up to a quad byte boundary
(LA1, LA0 = 11)
S
16-bit bus—8 words or up to a quad Lword boundary
(LA3, LA2 = 11)
2.2.2.2.2 Continuous Burst Mode (BTERM# “Burst
Terminate” Mode)
BTERM mode enables the PCI 9080 to perform long
bursts to devices that can accept longer than 4 Lword
bursts. The PCI 9080 generates one address cycle and
then continues to burst data. If a device requires a new
address cycle after a certain address boundary, it can
assert BTERM# input to cause the PCI 9080 to generate
a new address cycle. BTERM# input acknowledges the
current data transfer and requests that a new address
cycle be generated (ADS#). The address will be for the
next data transfer. If BTERM mode is enabled, the PCI
9080 asserts BLAST# only if its FIFOs become
FULL/EMPTY or if a transfer is complete.
Note: If the BTERM# input signal is asserted, the
BLAST# will not be asserted until the conditions
described above are met.
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